The PCLK is always input in slave FIFO. AFAIK there is no option to drive the PCLK out like the IFCLK at FX2.
In the GPIF II Designer, you can set the PCLK direction to be either driven by the FX3 or the external processor. It also appears as an option in one of the Slave FIFO Application Notes.
It sounds like the slfifosync example in the SDK is probably set up so that PCLK driven by the external processor, though? Can anyone confirm this? I really don't want to burn out an FPGA pin.