A few quick questions about cyfxslfifosync SDK Example:

[Anonymous]

I have a few quick questions about the Slave FIFO Sync example distributed with the SDK, v1.0.

       

    
1. How are the flags configured in the example?  What threads are they tied to?
    
2. As soon as I program the cyfxslfifosync firmware onto the FX3, both flags go high. Is this expected?
    
3. Is the GPIF II Designer file used to create the GPIF files for this example available?
   

       

Thanks!

[Anonymous]

 Just to clarify Question #2, I see FLAGA and FLAGB go high when the address pins = 00, and I see them go low when the address pins = 01.

       

I need to know what those pins are configured for in the cyfxslfifosync example so I can make sense of how to program the external processor on the other end of the Slave FIFO interface!  What hardware threads are they tied to, which one is for read, which one is for write, etc.,

[Anonymous]

 Anyone?