PSoC3 DMA setup

[Anonymous]

 Hello, could somebody help me in how to configure one DMA block (specially number of bytes per burst, and number of request per burst) to do this?:

   

I have one DFB outputting 16bit words at Fs (3KSPS)

   

Its EOC fires one DMA request ina DMA block

   

I want the DMA to transfer first Low byte (available in HOLDA_PTR) then HIgh byte (in HOLDAM_PTR) to one UART (UART_1_TXDATA_PTR)

       

I have tryied several configs, using one or two transfer descriptors, but I only get one byte out off the UART for every EOC.

   

See my last attempt (only sends out one byte):

           

uint8 DMA_3_Chan;

   

uint8 DMA_3_TD[1];

               

#define DMA_3_BYTES_PER_BURST 2

   

#define DMA_3_REQUEST_PER_BURST 1

   

#define DMA_3_SRC_BASE (CYDEV_PERIPH_BASE)

   

#define DMA_3_DST_BASE (CYDEV_SRAM_BASE)

           

/* DMA Configuration for DMA_3 */

       

DMA_3_Chan = DMA_3_DmaInitialize(DMA_3_BYTES_PER_BURST,DMA_3_REQUEST_PER_BURST,

   

                                                                                HI16(DMA_3_SRC_BASE),HI16(DMA_3_DST_BASE));

   

DMA_3_TD[0] = CyDmaTdAllocate();

   

CyDmaTdSetConfiguration(DMA_3_TD[0], 1,  DMA_INVALID_TD, TD_INC_SRC_ADR);

   

CyDmaTdSetAddress(DMA_3_TD[0], LO16((uint32)Filter_1_HOLDA_PTR), LO16((uint32)UART_1_TXDATA_PTR));

   

CyDmaChSetInitialTd(DMA_3_Chan, DMA_3_TD[0]);

   

CyDmaChEnable(DMA_3_Chan, 1);

           

Thanks,

   

Maxi Guzman

[Bob_Marlowe]

At very first sight: Both devices (Filter and UART) are CYDEV_PERIPH_BASE and not Sram as you coded.

       

Bob

[Anonymous]

 Hi Maxi, here are a couple of things that needs to be changed in your code.

   

1) What is the UART TX Buffer size ? If the size of the buffer if 4 or lesser, then the dest address should be 

   

#define DMA_3_DST_BASE ( CYDEV_PERIPH_BASE  )

   

if the size of the buffer is greater than 4, it has to be CYDEV_SRAM_BASE.

   

2) The primary reason why you are getting only the lower byte is becuase of the coherency not set properly. The DFB staging register coherency key byte should be set to the byte that is written last. The DFB Filter component sets the default coherency key as the High byte. It should be changed to middle byte as DMA reads or writes low byte followed by high byte in the staging register.

   

Refer to DFB[0..0]_COHER register to learn more about filter coherency settings (Refer to the TRM register book for details) /*Filter Coherency set to mid byte */ Filter_COHER_REG = 0x55;

[Anonymous]

Hi U2, thanks for your comment. I found this document on my hard driver. This App note does not seem to exist on cypress website anymore.