Hi,
I am working with the 2 address bit 32 bit data synchronous slave fifo example referenced in AN65974. I have an FPGA on the P Port and right now all it is doing is setting the address lines, A0 and A1, from 0 to 3 repeatedly. When I run the example I see Flag A and Flag B set to low. I then send 512 bytes from the USB Control center on the OUT endpoint and I see Flag B go high when the address is set to 1 or 3, and go low when it is set to 0 or 2. Flag A stays low at all address. Since for this example both Flag A and Flag B are set to current thread, I expected to see them track each other.
Is that assumption correct?
Also, the GPIF II help file says
sockets 0,4,8,12, etc., are mapped to thread 1. It’s thread 0 isn’t it?
sockets 1,5,9,13, etc., are mapped to thread 2. It’s thread 1 isn’t it?
Thank you for your help.
