COMP[Z] interrupt

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MiKO_283856
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 Hi to all,

   

Well, following my previous post (Freeing IOs) I need to open this new one, as it's indirectly related to.

   

Using now COMPZ as a ZCD in the design, I need to generate an interrupt on every change of its output (I mean going positive OR negative).

   

I've looked at the module and TRM datasheets but found nothing close to, and search in the forums didn't give me any clue. 

   

I'm thinking about switching/reversing the polarity of the comparator in the interrupt handler (before the starting of the next half period) but I'd like to know if there would be a cleaner way to do it.

   

Best regards,

   

Michel

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Bob_Marlowe
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Reversing the polarity of the input could lead to spikes & glitches and waiting is not really appropiate for a interrupt routine, but that depends on the frequency of the input-signal and the other jobs that the PSoC should perform.

   

 

   

Bob

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Bob_Marlowe
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I'd really like to have an "Edit" function in this forum....

   

The other approach could be to take a second comp-bus which input is tied to the same comp-output. You may select the polarity of the output by editing the LUT at the comparator output, but that will not work with every analog block (0 and 3 will work)

   

Bob

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MiKO_283856
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 Hello Bob,

   

I agree with the "Edit" button and the gliches, no way to use Comp-Bus 0, too much stuff in columns 0 & 1 linked together. Well, finally it seems that the original approach was the finest.

   

Unfortunately, it's not gonna help me to add the new functionnalities my customer asked me. May be I will have to switch to an extented package to shift the current digital routes (which are using analog pins) to a pure digital port, therefore freeing the analog IOs I need.

   

Thanks for your great help.

   

Michel

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MiKO_283856
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Still trying to find another track.

   

I'm not accustomed with the Row Digital Inteconnection Architecture and the TRM is a little bit hard to decypher at this point, but is there a possibility to use the the logical combinations of the RDIxLTx Register of the concerned Comp-Bus to XOR its current state with its previous value (which would have been latches by hardware or software) before triggering the result to the Int Controller?

   

However I don't know how.

   

Michel 

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Bob_Marlowe
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I would suggest: keep your hands off from accessing configuration registers and things like that if you can solve it in hardware, especially in time-tight interrupts. Not quite fit with the interconnections? Yes, I admitt it takes some time. Do not concentrate on the internal registers, bits and settings. I started the very same way when I began to dig through the TRMs. When I started to design (first with Designer, later with Creator as well) I realized that there was absolutely no need to know more about registers except for PRTnDR and some rather dirty tricks when they were well-documented by Cypress.

   

You want two interrupts? Then try to get two interrupts.

   

Have a look at the attached project (which primarly has nothing to do with your problem, I just changed one to my/your needs), concentrate on the analog section only and the settings of the comparator-busses0 and 3. Here you have two interrupts now, one for the rising edge and one for the falling. Use the interconnection in your project (have a look at the LTU of the comb-bus) and enable the two interrupts as usual.

   

 

   

Happy coding

   

Bob

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Bob_Marlowe
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Caught a flu, not quite fit! Here's the project

   

Bob

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MiKO_283856
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 Bob,

   

OK copy, will keep your advice in mind.

   

I understand the way it's done in your example, seems also to work with Comp-Bus2 (which holds the COMPZ in the design) & Comp-Bus1 (which is available for this purpose).

   

I guess the 2 signals are respectively managed by the corresponding Analogx bits in the Int regs (INT_MSK0, INT_CLR0). I also guess that if there are API functions available to manage the interrupt from COMPZ, I need to directly drive the bit in the INT_MSK0 for Comp-Bus1.

   

And finally the 2 Analog1 and Analog2 entries in the Vector Table hold by boot.asm should point to the same interrupt handler.

   

This is the way I understand the concept. Anything else about this?

   

Take care with the flu.

   

Michel

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Bob_Marlowe
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As I said before, you do not need to set any bits in any config-register is my experience.

   

The COMPZ-module DRIVES the comparator-bus 0 and 3 (in my example) simultaneously, thus generating the interrupts on rising and falling edge of the COMPZ. Of course the entries may address the same interrupt-handler without conflicts as far as you preserve the reentrancy scheme: NO access to ANY global var, no call to a non-reentrant function.

   

 

   

For further help it is always adviceable to upload your (current) project here. To do so:

   

Build->Clean Project

   

Zip (NOT Raw!) the folder and upload it here

   

 

   

Bob

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Bob_Marlowe
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I shouldn't post with fever,

   

your'e right, you have to define your comp-bus accesses yourself. Stick to the asm-file COMP.asm there you see the names and bitmasks used to en/disable and clear the interrupts.

   

 

   

Bob

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MiKO_283856
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OK Bob, sounds great.

   

Can't release the project, sorry, I'm under NDA.

   

However will keep the Community informed of success, it might help other people.

   

If not, will go on posting 

   

Michel

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Rolf_Nooteboom
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 Hi,

   

I do not quite agree with Bob to not use registers other than PRTxxDR. In fact, you can get much more out of PSoC if you do know about registers. However, you should know what you are doing.

   

In this case you can change the slope of the comparator bus by modifying the Analog LUT Control Register (ALT_CRx).

   

For example, you could put this in your Comparator interrupt routine:

   

if ((ALT_CR0 & 0x0F) == 0x03)                     // Is Comparator bus rising edge (A)? 
{
    ALT_CR0 &= ~0x0F; 
ALT_CR0 |= 0x0C;    // YES > Set Comparator bus IRQ to falling edge (~A)
}
else
{
    ALT_CR0 &= ~0x0F; 
ALT_CR0 |= 0x03;    // NO > Set Comparator bus IRQ to rising edge (A) 
}

   

Another option is to route the comparator bus trough a DigBuf component and connect it inverted to a free IO (invert by setting Row_x_Logic_Table_Select to ~A) or use the DigInv component. Next set an interrupt on this pin.

   

Probably  you could use the Digital block interrupt of the DigInv component also, although I never tested this.

   

 

   

Regards,

   

Rolf - Gold Design Partner

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MiKO_283856
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Hi Rolf,

   

Thx for this other solution, in fact I had already tested it (thru the use of an XOR instead of an IF) before you posted, but even with this or Bob's one, I've had no success in maintening the system functionning correctly.

   

The only way it currently works is thru the use of an external analog output pin which is configured HZ with the ChangeFromRead option. It triggers a GPIO interrupt each time the comparator switches, as requested. I guess there is possibly a timing delay or shift phase introduced by the input pin stage which allows the design to shift properly during the initial forced-state to steady-state transition time .

   

The system is a kind of closed loop controlled on the basis of  half a sinusoid (can't give more details), and driving it with the CompBus(es) and the associated LUT(s) didn't give me the behavior I expected. The goal was to release as many analog output pins as possible (and optimize the use of the Psoc internal resources) as I need to integrate further analog functions using the same chip.

   

I will come back on complementary tests using the analog colum interrupts as soon as I've been able to release a fully working prototype.

   

Michel

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Bob_Marlowe
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English is not my native language and probably I didn't express exactly what I ment to say.

   

Take the attached example, Download it to a PSoC1 3270 (3240??) kit, connect externally p0_0 with p0_2 and see the interrupts counting.

   

 

   

Bob

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MiKO_283856
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 Bob,

   

Your English is perfect, mine's certainly worse

   

Anyway I really unterstood well what you were suggesting, and this is exactly what I did.

   

I was able to receive correctly the interrupts, no problem here, even with Rolf's solution. No doubt on this!

   

However trying to launch the system this way was unsuccessful in spite of double-checking everything.

   

PSoC technology is very powerfull involving there are many (tricky) things which need to be well understood. I'm not new to the analog/digital world, however I'm a PSoC newbiz. The problem I'm facing at may be external to the PSoC achitecture however not being PSoC familiar leads me to dead-ends.

   

The previous guys who designed the system may have had this kind of problem, but there are neither notes nor documentation about the solutions they retained. As I'm acting as a re-designer (improving the integration to reduce the BOM and managing further options) without any doc except a schematic and an uncommented source file, I'm missing necessarily something somewhere. However as time's running I have to keep some previous solutions ... and this is a little bit frustrating.

   

Michel

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Rolf_Nooteboom
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 Hi Michel,

   

The idea to use a XOR to switch slope is even better 

   

Did you bring the COMPBUS out and watched it on a scope? Are there any glitches on it? Is your interrupt routine finished before the next one is started?

   

You may have to flip an output pin during the interrupt routine and see where it fails using a scope.

   

Regards,

   

Rolf

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MiKO_283856
Level 4
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 Hello Rofl,

   

I went thru all this. The 1/2 sinus period is rather slow (~600Hz) which give the IT controller and the soft handlers time to manage their jobs before the next rising edge arrives.

   

For the moment this is a mystery, but as I already said, as soon as the proto is ready, I will go on investigating. I need to understand what's going wrong, and the conclusion could be useful for the community.

   

In the meantime, I keep on working with the pin.

   

Stay tuned ...

   

Michel

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