1. The FX3 Slave FIFO firmware example works with this speed after changing the packets per burst to 8 oder 16. See my other posts for the changes.
2. The FPGA has to deliver the data at this rates. For speed tests simply pull the SLWR to low and set the correct fifo addr. The PCLK schould be 80MHz or higher to achieve 320MB/s in 32 Bit Slave FIFO mode.
3. The Host software. The example Streamer software can handle such data rates. There is no modification needed.
Thanks for your prompt reply.
I searched your msges in all fx3 device and found the last informatios.(my eyes tired...)
I changed my src(slavefifosync) as exactly you wrote, but failed.
FAILED means, the pc streamer program can't open the END point.
That's why I asked the program source itself.
SYNCFIFO PGM SRC itself want to be uploaded....PLEASE!!! PLEASE!!
epCfg.enable = CyTrue;
epCfg.epType = CY_U3P_USB_EP_BULK;
epCfg.burstLen = CY_FX_SLFIFO_PACKETS_PER_BURST;
epCfg.streams = 0;
epCfg.pcktSize = size;
if(CY_U3P_SUPER_SPEED == usbSpeed)size *= CY_FX_SLFIFO_PACKETS_PER_BURST;
/* Create a DMA MANUAL channel for U2P transfer.
* DMA size is set based on the USB speed. */
dmaCfg.size = size;
/* Super speed endpoint companion descriptor for producer EP */
0x06, /* Descriptor size */
CY_U3P_SS_EP_COMPN_DESCR, /* SS endpoint companion descriptor type */
CY_FX_SLFIFO_PACKETS_PER_BURST - 1, /* Max no. of packets in a burst : 0: burst 1 packet at a time */
0x00, /* Max streams for bulk EP = 0 (No streams) */
0x00,0x00, /* Service interval for the EP : 0 for bulk */
And in the header file:
#define CY_FX_SLFIFO_PACKETS_PER_BURST (16) //SuperSpeed Packets per Burst
You have to modify the size at all points in the firmware: USB 3.0 descriptor, DMA config, endpoint config. And you have to check if superspeed is enumerated, in 2.0 you must not set the burst length! With my posted code sniplets it works, I´m not allowed to upload any source code. Also you have to set the DMA mode to AUTO for maximum speed.