1 Reply Latest reply on Jun 6, 2012 11:53 PM by prajith.cheerakkoda

    define EP8 as OUT causes probleams  - FX2

    pascal.schwartz

       Hi 

         

      I am trying to define the EP8 as out in my FX2 (using the slave fifo)

         

      but when i send from the host block to EP8 the 'get config desc' hangs and the software is stuck.

         

      if i no write to EP8 it works. 

         

      here is the code

         

       

         

       

         

      void TD_Init(void)             // Called once at startup

         

      {

         

       

         

        REVCTL = 0x03; // MUST set REVCTL.0 and REVCTL.1 to 1

         

       

         

      IFCONFIG = 0x43; // use IFCLK pin driven by external logic (5MHz to 48MHz) slave fifo

         

      // use slave FIFO interface pins driven sync by external master

         

      SYNCDELAY;

         

       

         

       

         

      SYNCDELAY;

         

      EP2CFG = 0xEA; // sets EP2 valid for IN's  triple(x2) buffer, size 512, bulk

         

       

         

      SYNCDELAY;

         

      // EP4CFG = 0xE0; // sets EP4 not valid (ep2) for out, bulk

         

      EP4CFG = 0x00;

         

       

         

      SYNCDELAY;

         

      // EP6CFG = 0xE0; // sets EP6 valid for IN's, bulk, 512 double

         

      EP6CFG = 0x00;

         

       

         

      SYNCDELAY;

         

      EP8CFG = 0xA0; // sets EP8 valid for OUT 's , bulk

         

       

         

       

         

      SYNCDELAY;

         

       

         

      SYNCDELAY;

         

        FIFORESET = 0x80; // reset all FIFOs

         

      SYNCDELAY;

         

      FIFORESET = 0x02;

         

      SYNCDELAY;

         

      FIFORESET = 0x04;

         

      SYNCDELAY;

         

      FIFORESET = 0x06;

         

      SYNCDELAY;

         

      FIFORESET = 0x08;

         

      SYNCDELAY;

         

      FIFORESET = 0x00;

         

      SYNCDELAY; // this defines the external interface to be the following:

         

      SYNCDELAY;

         

      EP2FIFOCFG = 0x0D; // this lets the FX2 auto commit IN packets, gives the //8bit

         

      SYNCDELAY;

         

      SYNCDELAY;

         

      EP4FIFOCFG = 0x05; // this lets the FX2 auto commit IN packets, gives the//8bit

         

      SYNCDELAY;

         

      SYNCDELAY;

         

      SYNCDELAY;

         

      EP6FIFOCFG = 0x00; // this lets the FX2 auto commit IN packets, gives the//8bit

         

      SYNCDELAY;

         

      SYNCDELAY;

         

      EP8FIFOCFG = 0x00; // this lets the FX2 auto commit IN packets, gives the//8bit

         

      SYNCDELAY;

         

      // ability to send zero length packets,

         

      // and sets the slave FIFO data interface to 8-bits

         

      SYNCDELAY;

         

       

         

      SYNCDELAY;

         

      OUTPKTEND = 0x88; // Arm both EP2 buffers to “prime the pump”

         

      SYNCDELAY;

         

      OUTPKTEND = 0x88;

         

       

         

      // and defines the endpoint for 512 byte packets, 2x buffered

         

      PINFLAGSAB = 0x00; // defines FLAGA as prog-level flag, pointed to by FIFOADR[1:0]

         

      SYNCDELAY; // FLAGB as full flag, as pointed to by FIFOADR[1:0]

         

      PINFLAGSCD = 0x00; // FLAGC as empty flag, as pointed to by FIFOADR[1:0]

         

       

         

      FIFOPINPOLAR = 0x00; // set all slave FIFO interface pins as active low

         

       

         

       

         

       

         

      EP2AUTOINLENH = 0x02; // you can define these as you wish,

         

      SYNCDELAY; // to have the FX2 automatically limit IN's

         

      EP2AUTOINLENL = 0x00;

         

      SYNCDELAY;

         

       

         

      // EP8AUTOINLENH = 0x02; // you can define these as you wish,

         

      // SYNCDELAY; // to have the FX2 automatically limit IN's

         

      // EP8AUTOINLENL = 0x00;

         

      // SYNCDELAY; // out endpoints do not POR (power-on reset) armed

         

       

         

      // SYNCDELAY; // out endpoints do not POR (power-on reset) armed

         

       

         

         // Set the fifo programmable level of EP2

         

         // Set level to 3 packtes  +  1024*3+992 = 4064 (out of 4096)

         

        /* EP2FIFOPFH = 0x1B;

         

         SYNCDELAY; 

         

         EP2FIFOPFL = 0xe0;  */

         

       

         

      EP2FIFOPFH = 0x0B;

         

          SYNCDELAY; 

         

          EP2FIFOPFL = 0xE0;   

         

       

         

       

         

      SYNCDELAY; 

         

      SYNCDELAY; 

         

       

         

       

         

          EP1OUTCFG =0xA0;

         

          EP1INCFG  =0xA0;

         

      SYNCDELAY; // out endpoints do not POR (power-on reset) armed

         

       

         

       

         

         EP1OUTBC = 0x40;              // arm ep1out (warning: only 64 bytes deep)

         

         EP1INBC = 0x40;              // arm ep1out (warning: only 64 bytes deep)

         

      }

        • 1. Re: define EP8 as OUT causes probleams  - FX2
          prajith.cheerakkoda

            Hi,

             

            The buffer configuration that you have used is invalid, please go through section 1.17 EZ-USB Endpoint Buffers of TRM for valid buffer configurations.

             

              For a bulk endpoint the FIFO buffer size needs to be set to 512  bytes and not 1024 bytes. As per  USB 2.0 spec the  maximum packet size of a bulk endpoint is restricted to 512 bytes and  the data is transferred over USB in packets of 512 bytes maximum.  So, in order to maintain  conformity, the endpoint size in the FX2LP must be configured for 512  bytes, please look into EP2 buffer configuration

             

           

             

          Thanks 

             

           

             

          Prajith