4 Replies Latest reply on Jun 22, 2012 12:51 AM by olaf.petzold

    possible Verilog a1_init_a macro bug

    olaf.petzold

      at this time I wrote a DP verilog implementation and need to set A1 with a value != 0. If I check the Sim in Modelsim it is always 0. Can someone confirm this? My lines are shown here :

         

        ...

         

         cy_psoc3_dp8 #(
                        .a0_init_a(TRESHOLD_ZERO),
                        .a1_init_a(8'd8/*TRESHOLD_POS_ON*/),
                        .d0_init_a(TRESHOLD_NEG_OFF),
                        .d1_init_a(TRESHOLD_POS_OFF),
                        .cy_dpconfig_a(dpconfig0))
         DP8 (  ...

         

       

         

      If it realy a bug, how fast will it be fixed and distributed with the next update. Or even is there a work arround?