Hi, I've exactly the same problem. I’m controlling the GPIF interface by means of an FPGA. As a first attempt I used the SynchronousSlaveFifo stuff provided by Cypress with just CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT set to one in order to enable the 32 bit interface.
If I correctly understood the documentation and the comments in the code, to stream data from the device to the host in the SynchronousSlaveFifo firmware I have just to set:
Addr[0,1] to 0 in order to permanently select thread 0 (device to PC stream) and
SLCS : ‘0’
PKTEND: ‘1’ (no short packets!)
With the above configuration (I know that neglecting flaga/b I’ll lose some data when fifos are full, but at the moment I don’t care about this, I just want to see the example working ) when I run the Streamer application provided by Cypress and I connect it to the In endpoint I would expect that data is streamed form device to the host.
Unfortunately this doesn’t happen. I only get USB read timeouts.
All the signals have the correct value on the FX3 including th PCLK (verified with an oscilloscope).
Are the above statement correct ?
Does anyone had success on using the SynchronousSlaveFIFO example as is ?
Do I missed something on how I’m handling the FX3 signals ?
Thanks in advance, Joel
Sorry I did a mistake... things are working now...
Which data transfer rates can you achieve using the 32 bit slave fifo. Does the slave fifo work correctly with multiple packetes per burst?
What was the mistake that you did and how it is working now.
Could you please share with us.