7 Replies Latest reply on Jul 3, 2012 8:44 PM by rama.sai.krishna.vakkantula

    DMA buffers


      Hello. In the Slave FIFO example, the dmaCfg.count is set to 2 (Slave FIFO channel buffer counts 2). When the data is transferred from U to P, the data is written to the first buffer at the first time and written to the second buffer at the second time. After that, if the Reading from Slave FIFO (SLRD) is not active, the buffer will be always full and no more data can be written. Once the Reading from Slave FIFO starts, the buffers will be clean and ready for the next transfer. Is my understanding right?

          I also want to use I2S to transfer short command to FPGA, but I can not find such firmware example. Could someone give me some suggestions?   
          Lehua Chen