1 2 Previous Next 18 Replies Latest reply on Jul 9, 2012 7:01 AM by lehua.chen

    Maximal PCLK frequency in Slave FIFO Sychronous

    lehua.chen

      Hello, I try to supply the PLCK with 80MHz sine wave. When I click Transfer Data-In in USB control center, at the first several times, the transfers are correct. Then it will show “BULK IN transfer failed with Error Code: 997”. It does not happen when the PCLK frequency is below 50MHz (throughput: 136MB/s).

         
          My setting is as following:   
         
          epCfg.burstLen = 15;   
         
          dmaCfg.size = size*15;     
         
          0x07,  /* Max no. of packets in a burst   
         
              
         
          My questions are:   
         
          (1), Is it possible to supply PLCK with sine wave at maximum frequency (eg: 80MHz)? It seems the sine wave is the same as square wave as a clock, because only the rising edge is used.   
         
          (2), In the manual, it mentions “programmable 100-MHz GPIF II interface”. What is the maximal throughput if PCLK is 100MHz. How should we set the burstLen, dmaCfg.size and Max no. of packets in a burst?   
         
          (3), In the Readme.txt in USB BULK SOURCE SINK EXAMPLE, Having only 1 endpoint (IN or OUT) is recommended. So if I only want to use Endpoint In, is it necessary to delete endpoint OUT?   
         
          Best regards,   
         
          Lehua Chen   
        • 2. Re: Maximal PCLK frequency in Slave FIFO Sychronous
          ramav_01

           Hi Lehua Chen,     

           

             

          Below are my answers/suggestions:     

           

             

           

             

          (1), Is it possible to supply PLCK with sine wave at maximum frequency (eg: 80MHz)? It seems the sine wave is the same as square wave as a clock, because only the rising edge is used.     

           

             

          I would recommend you to use a square wave. Square might be giving little bit more time for GPIF to sample data in.     

           

             

          (2), In the manural, it mentions “programmable 100-MHz GPIF II interface”. What is the maximal throughput if PCLK is 100MHz. How should we set the burstLen, dmaCfg.size and Max no. of packets in a burst?     

           

             

          I don't have the exact number. But GPIF II interface is well tested at 100MHz synchronous.     

           

             

           burstLen, dmaCfg.size and Max no. of packets in a burst - should be same as it is described in the USBBulkSourceSink example.     

           

             

          (3), In the Readme.txt in USB BULK SOURCE SINK EXAMPLE, Having only 1 endpoint (IN or OUT) is recommended. So if I only want to use Endpoint In, is it necessary to delete endpoint OUT?     

           

             

          Yes. Comment out the code related to endpoint OUT in all the places.     

           

             

          I have the source files that are optimized for USBIsoSourceSink example. You can use them as a reference here.     

           

             

           

             

          Regards,     

           

             

          sai kirshna.     

           

          • 5. Re: Maximal PCLK frequency in Slave FIFO Sychronous
            ramav_01

            It seems there is some issue with attaching files....

            • 6. Re: Maximal PCLK frequency in Slave FIFO Sychronous
              lehua.chen

              Hello, sai Krishna,

                 
                  I change the settings as recommended by you. But it still does not work at 80MHz. I find when burstLen=15, dmaCfg.size=15 and Max no. of packets in a burst=0x00, I get successful transfer in Streamer. But several seconds later, it only receives only failures.   
                 
                      
                 
                  In the Readme.txt in USB BULK SOURCE SINK EXAMPLE, it is said while changing dmaCfg.size, make sure there is enough memory available for buffering. What is the “memory” means here? How can I set this value?   
                 
                      
                 
                  Thank you,   
                 
                  Lehua Chen   
              • 7. Re: Maximal PCLK frequency in Slave FIFO Sychronous
                ramav_01

                 Hi,

                   

                Do the following things:

                   

                1. Keep only one endpoint. In your case IN endpoint.

                   

                2. #define CY_FX_EP_BURST_LENGTH          (15)     /* Super speed burst length in packets. */

                   

                3. Once you change CY_FX_EP_BURST_LENGTH, then it will be updated in the following places:

                   

                 

                   

                epCfg.burstLen = CY_FX_EP_BURST_LENGTH;

                   

                 

                   

                dmaCfg.size  = (2*1024 * CY_FX_EP_BURST_LENGTH); and 

                   

                in the descriptors, 

                   

                 

                   

                 /* Super speed endpoint companion descriptor for consumer EP */

                   

                    0x06,                           /* Descriptor size */

                   

                    CY_U3P_SS_EP_COMPN_DESCR,       /* SS endpoint companion descriptor type */

                   

                    (CY_FX_EP_BURST_LENGTH - 1),    /* Max no. of packets in a burst(0-15) - 0: burst 1 packet at a time */

                   

                    0x00,                           /* Max streams for bulk EP = 0 (No streams) */

                   

                    0x00,0x00                       /* Service interval for the EP : 0 for bulk */

                   

                 

                   

                Regards,

                   

                sai krishna.

                • 8. Re: Maximal PCLK frequency in Slave FIFO Sychronous
                  lehua.chen

                  Hi, sai Krishna,

                     
                          
                     
                      I exactly changed the setting as you suggest. I can not understand why the transfer successes only for short time and then it fails. It seems it is limited by some buffers.   
                     
                          
                     
                      Thank you   
                     
                      Lehua Chen   
                  • 9. Re: Maximal PCLK frequency in Slave FIFO Sychronous
                    ramav_01

                     Hi,

                       

                    Are you using Ivy bridge?. What is your host controller.

                       

                    Regards,

                       

                    sai krishna.

                    • 10. Re: Maximal PCLK frequency in Slave FIFO Sychronous
                      lehua.chen

                      Computer:

                         
                          Intel(R) Core(TM) i5-2520M     CPU@2.5GHz 3.35GB RAM   
                         

                      Thanks

                         

                      Lehua Chen

                      • 11. Re: Maximal PCLK frequency in Slave FIFO Sychronous
                        ramav_01

                        Hi Lehua Chen,

                           

                        We are seeing some issues with Intel Ivy bridge architectures and we are working on it.

                           

                        I am not sure whether your chipset is part of that.

                           

                        Anyways, the best thing to do is to create a technical support case by attaching the USB trace during the error condition.

                           

                        Thanks,

                           

                        sai krishna.

                        • 12. Re: Maximal PCLK frequency in Slave FIFO Sychronous
                          lehua.chen

                          Hi, sai Krishna,

                             
                                  
                             
                              I found the wave shape distorted a lot at the PCLK when the frequency is above 50MHz. I think this is the reason that the Slave FIFO Synchronous test did not work well when PCLK=80MHz. Now I used a buffer between the clock source and the PCLK pin, but the distortion does not change better. Maybe it is due to the limit of the diodes in the PCLK pin (capacitors). Does it also happen when you test the GPIF with 100MHz?   
                             
                                  
                             
                              Thank you   
                             
                              Lehua Chen   
                          • 13. Re: Maximal PCLK frequency in Slave FIFO Sychronous
                            ramav_01

                             Hi Lehua Chen,

                               

                            Did you get a chance to check the traffic on the USB bus to understand what exactly is happening.

                               

                            May be the oscilloscope is not capable of probing a signal that runs at 80MHz. Please check that one as well.

                               

                            Regards,

                               

                            sai krishna.

                            • 14. Re: Maximal PCLK frequency in Slave FIFO Sychronous
                              lehua.chen

                              Hi, sai Krishna,

                                 
                                      
                                 
                                  Thank you for your reply.   
                                 
                                  The sampling speed of our oscilloscope is 2.5GS/s and the measurable maximum frequency is 300MHz. The probe is original one with maximum frequency of 500MHz. The range for our signal generator is 5KHz to 1.5GHz (only sine wave). When I check the signal from the signal generator, it is perfect.   
                                 
                                      
                                 
                                  At present, we do not have the USB analyzer. It is not easy for me to check the traffic on the USB bus.     
                                 
                                      
                                 
                                  Thank you   
                                 
                                  Lehua Chen   
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