1 Reply Latest reply on Jul 11, 2012 6:42 AM by userc_39074

    About slave fifo clk



      In Slave firo sync operation, while the SLWR is asserted, data will be written into the FIFO, on every rising edge of the CLK and the FIFO pointer is incremented. 


      Here my question is that, is there any option to sample the data from data bus on the falling edge of the CLK.