Could you please give more details on this problem.
What is the master device that is connected to FX3 and I am assuming that you are using the example firmware (SlaveFifoAsyc) directly without doing any changes.
On the master side, assuming that you are writing a short packet to the slave then you need to assert CS (chip select), WR (write) and the PKTEND signal.
1.The master device is FPGA
2.i use only one thread in the firmware to get date from the fpga,and both the flag a and b are configgured to indicate the status of the currently addressed thread.
3.of course,i asserted CS,WR and PKTEND signal.
my question is why the input pktend signal can affect output Flag signal.
In SlaveFifoAsync example, the flags will be indicating whether the socket buffer on the slave side is full or not in the case of write from master. Master continuously write till the flags say that buffer is full. That is why here in case of shart packets, you are not seeing any change in the flag status.