2 Replies Latest reply on Jul 19, 2012 9:52 AM by anandsrinivasana_

    Confused about VBUS Connection from USB Connector



      I am using Cypress FX2LP in my interface design with Xilinx Spartan3 FPGA.. Based on Xilinx reference design schematics (from Digilent Nexys-3 Board and Xilinx Spartan3 Evaluation Kit), I found that VBUS from the USB connection may be left floating for self powered designs.


      I left VBUS Pin from USB connector as "no connect" and connected wake pin of FX2LP on GPIO of FPGA. On the custom board, I found that FX2LP will not appear in the System Device list unless I pull the WAKE line HIGH from FPGA. Therefore, I pulled the FX2LP wake line high. Since then, I apparently had no problems with my design, except, once in a million times, I have to perform a power cycle as the device won't show in the system devices.


      Recently, I came across Cypress AN15813, that states that monitoring the VBUS signal is very important and must be used in conjunction with wake line on FX2LP.


      My Question is:


      1- Is it mandatory to monitor VBUS line in self powered mode while using FX2LP in Slave FIFO Mode, I did not find such connectivity in XIlinx based Reference Designs?


      2- Can FX2LP drive D+/D- lines if wake pin is driven high in Slave FIFO Mode, while nothing is driven by the FPGA controller on the data lines, and WAKE pin is pulled up?