PSoC5 has both SAR and Delta Sigma.
i have an application which requires accurate data of 8 bits(6th bit from MSB determines a level).
-- so you require a reproducable resolution of 7 bit!?
Which is accurate whether the SAR or Delta Sigma.
-- any chance you want to look at the specs? Both can easily fulfill the requirements you listed
As well tell me is it better to make single ended or diff with one end connected to Vref=0.
-- ??? what does your signal look like
And further can i implement a SAR ADC using the components available in PSoC5(sample and hold, comparator, register)
-- besides the fact that it is a waste of resources, you could easily create a guess-converter, guess that should be a high or guess that should be a low level. Never tried it but I have a strong hintch the answer is "not really"
-- If you need faster conversions, it is the SAR, if you want to achieve a compatible design with a PSoC 3, use the Del Sig, if none of this matters, use the SAR, it is simpler.
If it is a yes/no decision only, why not using a comparator? Otherwise, it doesn't really matter which ADC you use. The DelSig ADC can give you higher resolution on the price of lower sample right (compared with the SAR ADC). Apart from that, they basically have the same requirements with regards to what they consume from the internal resources (the DelSig ADC needs more flash memory).
If you need a lower sample rate, using the DelSigADC is simpler, because it can handle down to 10sps in free-running mode. If you want to do that with the SAR ADC, you need an additional timer (with an attached clock) to trigger the conversion, because the SAR ADC clock cannot be lower than 1MHz.
A single-ended ADC is, basically, the same as as a differential ADC with one input connected to ground. Use the single-ended one, it saves you one pin :)
There is a wealth of stuff pertaining to A/D architectures and error analysis on the web.
Many vendors, TI, D, Intersil, NSC, BurrBrown (TI),......
You have to perform an end to end error analysis of all signal path components. Drift, offset,
non-linearity, PSRR, CMRR, thermoelectric board effects, the list is wonderful.
The tradeoffs are vast and varied. Job security.
So you start with a design goal, consisting of
5) Front end, pre conditioning
7) Galactic star to star collisions
Then start summing up all errors and comparing to design goals.
Here is a fraction of the reading one must master if claims of performance are to be believed -
1) Start by using scope on infinite persistence, and look at supply rails to see how much
pk-pk noise you have. Then look at noise BW with a spectrum to see what major contributing components are.
2) When you run A/D consider shutting off other timer/counters to reduce noise contributors.
3) Same as 2, if driving hi current loads like LEDs, 7 seg displays, heavy C loads, shut that I/O activity off.
4) Not all capacitors are equal. Look at actual Z vs f curves. Polymer tantalums for bulk much better than electrolytic or regular tantalums. Use caps with low lead L. Bypass always with bulk + ceramic s(.1 and .01 uF).
5) Split grounds and analog grounds and rejoin as close to power source as possible.
6) Scope on infinite persistence, look at clock oscillator phase noise to establish if excessive.
7) Band limit the signal chain.
8) Use external reference ground/bypass cap.
9) Reduce hi-z nodes to low z where possible to minimize noise pickup.
10) Some references
Reading for the afternoon :)
If you can take a 12M email file I can give you a lot of great material.