I am not sure if GPIF Designer is the right tool for our application. One of my colleagues used this tool and gave up after a lot of frustration. His problem was that when it did not work it was difficult to debug the generated code.
Since our application is so simple I thought that this could be done more easily. The sampling rate of the ADC is only 1MSps. If RDY0 or RDY1 is high we have data.
#define I_OR GPIFREADYSTAT & bmBIT0 // output ready for I
EP2CFG = 0xFA // Valid, In, Bulk, 1024, double
EP2FIFOCFG = 0x01 // wordwide
In TD_Poll // Pseudo code
If I_OR then Read port B and D to fifo
I thought that with an autopointer this will automatically be incremented and when the fifo was full a message was send to the host for xfer of data.
Is this a strategy that you won’t recommend?
Yes, it is possible that way. In that case you will have to use FX2LP in Ports mode, i.e. both Port B and Port D will be all GPIOs. If the data bus you want between FX2LP and ADC is not bidirectional, then this is possible. You can configure PortB and D as all Input pins. You can refer and modify the firmware inside "FX2LP Back To Back\Firmware\Manual Mode\slave" from http://www.cypress.com/?rID=45850. the summary of changes that you will hav eto do is as follows:
For making FX2LP come up in Ports mode,
IFCONFIG[1:0] = 00
For making Port B and D as all IN GPIOs:
OEB = 0x00;
OED = 0x00;
For reading the data, you may have to use something like (in TD_POLL() ):
for(i =0; i<1024; i++)
EP6FIFOBUF[i] = IOB;
EP6BCH = 0x04;
EP6BCL = 0;
Since the 8051 comes in the data path, the throughput will be greatly reduced. That is why I suggested GPIF for this. If you donot have such a limitation you can use Ports mode.
Thank you for your help.
I have looked through it again and it seems as if the port mode will not work. If the cpu is running at 48MHz and if every instruction requires four clock cycles, there is only 12 instructions for every sample (actually two samples since we have two channels). I guess that this is very few instructions in the TD_Poll().
This is our connection. We have two ADCs (I and Q) followed by 16k fifos. These fifos should be read by the usb-chip. The fifo empty flag is connected to the RDY-pins. I_EF = RDY0 and Q_EF=RDY1. The fifo data output is 3T and controlled by PA1=I_OE=Q_OE, selecting which fifo to read. The CTL0=I_REN and CTL1=Q_REN. The fifo holds more than 16ms of data, which means that it does not have be read very often. But the rate should be high. The plan is to read the I-data to Endpoint 2 and the Q-data to Endpoint6.
I thought that it should be possible to use auto mode and have an asynchronous read process running that could read the external fifo until it was empty and fill up the Endpoint fifo and automatically transfer the data to the host. Things may not be that easy.
I have spent a day working with the GPIF Designer. Immediately it is not that obvious how to use this tool when your application is very different from the example with writing to the fifo and reading the data back again.
Please create a tech support case at http://www.cypress.com/ -> Support-> Technical Support -> Create a case, so that one of our engineers can guide you on how to use GPIF to suite your application.