SR F-F's of course pretty easy, 2 gates will do it.
J-K, 6 gates, but I agree, if so simple should be in library.
PS : Or I should read the component authoring guide.
This sounds like a perfect project to make your first component and share it with the community. Our fine engineers are working on more complex components to enable you and all PSoC users creating new solutions with new functions all the time without changing your chip.
It's not that our engineers are lazy, they want to provide maximum value to you and the community!
Yes, Robert, you are right! I just started to watch this video https://secure.cypress.com/?rID=40327 and followed the instructions within Creator 2.1. And lo! I managed to create my very first component. Couldn't stop, so I created some more, have a look at the project
FlipFlops.cywrk.Archive01.zip 478.2 K
Simple but very usefull modules. Many thanks.
To be honest, I did not want to provide the community with new modules, I wanted to point out how easy it is to create own ones. I really started the video, stopped it when something was done and followed it up in Creator ... and so on. It was really a few minutes job to do the first steps until I received something functional. I just can suggest you to give it a try!
Robert: I never said your engineers are lazy, read what I wrote carefully. It is I who is lazy. Well, lazy but more importantly, rather incompetent. I'd rather get someone else to do it who is sure they haven't created a logic race or implied register (in Verilog).