Use port 3 pins appropriately for the Opamp_2. That will work. When u r using two opamps in the same quadrant, what happens is u r not able to use the AGL_4 line to feed to the DelSigma ADC. Change that to the right side quadrant,such that you can use the output of it to feed the delta sigma adc. This will now remove your routing problem. This is not the problem with PGA.
In Creator 2.1 there is an analog routing viewer, on the cydwr tab.
I do see the error, after quite a few clock binding errors. Still looking at project.
Hi people, i solved that problem. just change the port configs for the opamp_2. use port 3 which is in the other quadrant. There ll be no problem then.
Thank you rahulram and danaaknight, you guys are great, that was really fast response and solution.
I used R's solution with port 3 and it worked. Unfortunately, I actually wanted to mux my 2 op amps to the Del Sig ADC. Plus I had other intentions for one of the other OpAmps.
I tried to study through the Analog routing chapter of TRM and have come out baffled. I understood enough to figure out to hardwire all my OpAmp output routes externally to my mux inputs.
Thank you for the tip Dana concerning the analog routing viewer, I will upgrade to Creator 2.1.
What are clock binding errors, where do I see them, and what can I do about them?
Always wanting to learn more, I love these chips almost as much as kettle cooked ones.
Best regards, Bruno.
When you do a compile, select "view" menu item, then "other windows", then "notice" list.
In that view, you can double click an error marked with a red X, and it will show you on
schematic where the error is.
I do not know what the binding errors are, I myself need help on this. I did see antoher thread
where a clean and compile cleared all the errors.
Notice list is also a tag at the far bottom below your output. I have been seeing a lot of stuff there but never bothered to clean up. Eventually I will put some more effort if ever I get stahled because of something there.
I'd like to attract attention to the front end of my project. I found that using an unsynchronized tachometer signal to trigger a capture input to a timer sometimes caused erroneous values which were followed by good values as if nothing had gone wrong on the previous capture. I tested whenever there was an erroneous value, read it again. this gave me a copy of the erroneous value. That means that the error occurs at capture time perhaps coincidental with the clock. The perfect fix is to place a D flip-flop clocked by the falling edge of the bus clock. That way the read and the capture always happen half clock cycles apart. It's now beautifully clean. I just want others to know this trick but don't know where to post it efficiently.
Thanks again, Regards,