You always have the option of using logic gates (Eg: a pair of nand gates) and flip-flops to create a switch-debounce circuit.
There is a "Glitch filtering' component in the library.
Use an SR latch that resets itself after running an 8 bit one shot down counter clocked at say 2.5 kHz, with it reseetting itself on TC. That gives you 100 ms of delay between allowed swtich firings. An SR latch is just two NANDs or NORs with cross feedback.
Have a look into the datasheet of the "glitchfilter"-component and see how it works. It's using some resources, so its principle of operation can be adapted to your needs:
You need a clock to timeout your stages.
When a keypress is a logical 1 (High) you may use 2 - 3 DFFs chained together and async reset by the negated switch input. Thus the output of the last FF is normally 0 and switches to 1 after n clock cycles (where n is the number of FFs) the switch is held High.
How many switch inputs are you trying to debounce ?
The SR approach requires either a supporting timer or schmidt (with R-C network to
work properly). The glitch filter uses LUT + 3 D's. Resources required per pin.
One of the principal advantages of a SW solution is ease of handling many pins with
one main piece of HW, a timer, and some code space.
If if absolutely has to be HW only, here is an approach -
Keep in mind a schmidt can be a comparator with hysterisis. Also possible a NI buffer with
fdbk R's around it, but you have to be careful about building an oscillator due to stray C.