Here is an issue I came across on the dev kit for PSOC5 (I think it is ES1). I have mostly resolved it by changing routing internally, but am throwing it out here in case its useful or anyone has any insights.
I have an input square wave signal that is variable in frequency and I need to sample this to determine the result of the instrument (a gravity meter). This particular frequency is on the order of 7 kHz and needs to be resolved to 0.005 Hz. I can take a couple of minutes to arrive at this resolution.
I decided to "clean" the signal by running it through a comparator, so I chose one of the SIO pins with a voltage comparison. The nice thing here is the signal becomes a great looking square wave that is synchronized to the internal bus clock. I used an external OCXO (26Mhz) as a frequency input to a pin just to get that extra bit of precision (used this as masterclock). To arrive at the frequency with minimal noise, I tried many different peripheral arrangements, but I can get to those later, as depending on timer/counter/capture/trigger routing etc, there was additional "noise" added.
The interesting thing about using the SIO as the input was it introduced frequency "noise", I guess it could be called jitter. It did not matter what reference voltage I chose. The syncronized squarewave that came out of this arrangement had lots of error (i really can't recall how much). I don't know if this is related to the voltage reference being slightly unstable, or the internal comparator being slow or something else
This I was able to mitigate by changing the routing. Turned out that from trial and error I got the best results by using an analog input pin, followed by an opamp buffer. This signal was fed into a comparator with 0.256V reference, and following this the output was fed into a sync component.
This arrangement gave me much better jitter probably 10 times better (lets say 90% of the time)
Now of course I am wondering can I get into one of the components and use an non-synchronized (dangerous!) clock signal...