The flash limit of 64K is caused by the 8051 core structure. Pointers are only 16 bit wide, the upper bytes of a pointer are used to specify to which memorty area it points to.
30% used already? 10% was used to program the hardware (components) another part is the firmware for the used components which is not a small amount.
70% free for a user interface can be sufficent, I would be more optimistic.
It's quiet normal the first 20K is used up quickly. This has to do with component api's and included Keil libraries. For example the DeltaSigma ADC component already uses almost 4K of flash.
When I started using PSoC3 I was amazed also how quick the first 30K was used. But, as all components, libraries and startupcode already are placed in flash, you will see how long it takes before you use up the next 10K.
You also have EEPROM you can use for GUI or settings. And only 'bare' code doesn't consume much.
Much thanks for the consensus. So maybe no "push to shove" afterall.
Yes I recall a number of FPGA usages where I quickly got to 65-70%, but years later never was able to fill it up, or not route it.
And good tips too for later.