2 Replies Latest reply on Aug 22, 2012 8:37 AM by user_78878863

    Generate for multiple pins component

    user_1377889

      I tried hard to understand the "Component Author Guide" but some things are not quite clear to me:

         

      When I want to design a component that uses several I/O pins and the number of pins should be parameterized in the configuration dialog

         

      1st. How to generate in Verilog (or is there a better/easier way?) the pins

         

      2nd. How to set the properties of the pins (even if they are all the same) 

         

       

         

      Regards, Bob

        • 1. Re: Generate for multiple pins component
          user_78878863

          The only hint I can see is part 3.6.3 - 'advanced shape properties'. It says there is a 'visibility expression' for terminals, which define whether a certain terminal is visible or not. This means you would need a component property for the number of terminals needed, and then have for each terminal a test whether it is included or not.

             

          You may want to look into the CyControlReg_v1_70 folder of your Creator installation - it contains the verilog code for the control reg, which shows how to handle a variable number of terminals. Judging from what I can read in CyControlReg_v1_70.cysym, it works as described above (with the addition of checking for the need to display as a bus).

          • 2. Re: Generate for multiple pins component
            user_78878863

            Oh, make that 'part 3.6.2' - stupid keyboard :)