As far as I know there is no limitation except the number of channels (24)
All DMA has to be served by the DMA-controller and all transfers have to pass the PHUB and the CPU is going to access the system busses at the same time. So there is room enough for some bottlenecks which may disturb the parallelism of 23 concurrent DMA-channels.
The PSoC5 architecture TRM (http://www.cypress.com/?docID=36586 ) explain it nicely (chapter 6). There are 24 DMA channels available, so you get only 24 configurations which can be active (when you create a TD, a channel gets assigned, and if none are left you get an error).
Each channel has an assigned priority (0..7), and lower priority wins (but this can be configured, see part 184.108.40.206 in the TRM). Within the same priority, round-robin is used, so all channels get executed in a fair manner.
So if you have too many DMA activity going, you might see delays, but no DMA will get completely blocked.
If the channel priorities are the same and all DMA channnels have been assigned, then is there a possibility that the DMAs can get stuck at some point....
1) And what happens if 2 DMA channels of same priority and having same source adddress and different destination address are started at same time....is there a possibility of getting stuck.
2) When the burst count is set as '0' - which means the breaking of data bytes is not carried out and entire transfer is completed in one shot then is it possible that we see some DMAs getting stopped (DMAs have same priority)..or will they be served one after other...
If with "getting stuck" you mean that the DMA subsystems runs into a deadlock and does nothing - no this, won't happen. What happens is that a DMA transfer will get delayed, because another one is executing.
When two DMA requests with the same priority are requested, the one with the older 'has not run' time wins. If both times are the same, the one with the lower DMA channel number runs first.
A DMA transfer already runing won't get interrupted - this will only happen during the setup phase ("source engine phase"). A TD will always run a complete transfer otherwise - even when then a higher priority DMA request needs to wait then.
Again - read the Architecture TRM, it explains this in much more detail (its 10+ pages about DMA).
ok......thanks a lot.....
And will i be able to connect nrq to isr and trigger interrupt at the end of transfer...I am having problem with this .....