As per my understanding, following is your setup.
FPGA --> FX2LP acting as slave --> PC.
If you are just concentrating on transferring data from FPGA to PC then you could do the following thing. You can connect FIFOADR1 to High and FIFOADR0 to 0/Ground, if you are planning to use the same example project without modifying.
Otherwise, if you are going to modify the firmware so that EP2 acts as an IN endpoint then you can connect those to pins to Ground.
Please let me know if that does not solve your problem.
Thanks for you repy,
what should I modify in the AN61345 uvision project file to set EP2 as an IN endpoint? Do you recomend the fx2_trm as the best reference for making these sort of modifications?
In my verilog code I've permanently deasserted the read and fx2 fifo output enable bits, and permanently asserted the fx2 fifo write bit. I'm using a virtex 4 and havnt yet ported over the hdl code supplied in the example to try.
In the AN61345 firmware I switched the configuration values for EP2 and EP6, and changed EP6AUTOIN to EP2AUTOIN.
I'm not seeing any data in my input buffer when I make a asyncrounous transfer as outlined in the cyapi programers reference.
Hmm this is tough, maybe I should slow down and take a step back to figure this one out (if only I had the time)
Thanks, any advice is appreciated