In a 5 V system, 12V, 1/2 lsb = ~ .6 mV. In my opinion anything < 5 LSBs pretty good
in a mixed signal design. One method of looking at noise, pk-pk, is scope on infinite
persistance, and watch the supply rails.
You might look at PSRR and nosie specs on regulators, in a 12 bit system they may be
significant. Also type of caps you are using.
Some useful references -
All AtoD Error.zip 12.1 MB
5 LSB?! If I got 5 LSB of noise I would consider that to be a complete disaster!
Nevertheless, is there anything you can see on the layout that might be affecting the S/N ?
Also, if a PSoC can't be expected to achieve more than 10.5 ENOB, why do some have a 16-bit ADC?
Will a 16-bit ADC have only 1.5LSB noise, and therefore achieve 14.5 ENOB?
I think dana meant '5 counts', which is more like 2.5 bits. Given that 1 bit means 0.6mV, this would be a noise of about 3mV.
Oh, and regarding your original question: there is AppNote AN57821 - PSoC3 and PSoC5 Mixed Signal Circuit Board Layout Considerations ( http://www.cypress.com/?rID=39677 ) which should help you. It explains what is needed for achievinbg even 20bits performance.
(Its difficult to tell from the image, since one cannot see the components, but I would guess you didn't separate the PSoC supply and the ground signals into a digital and a analog domain. This would mean that changes in the load introduce noise voltage spikes on these signals - and on ground they are deadly for precision)
I actually meant 5 lsbs. If you look at a typical board environment,
often you will see 200 - 400 mV noise on supply rail, and if you
do not separate A and D grounds, joing them at a single point of entry,
at board edge, you are asking for trouble.
Its not a PSOC issue, its a system issue. How many people do an end to end
noise, offset, temp, PSRR, thermo budget in a design. Few I would posit, except
the HPs and Tektronix and Marconis of the test world. How many actually look at
C ESR curves and SPICE simulate the power environment ? Its my personal belief
a lot of stuff gets put out there stating "I have 20 bits" but nowhere to be found is
nosie and actual accuracy and drift. Thats because when you try to do a full 12 bit,
1/2 LSB over all error and temp and V, you suddenly discover how difficult that actually
Take a look at the ploymer caps, they are an order of magnitude better ESR vs F
for bulk needs. And C behaves a lot better with V.