The capture signal stores the timer-value in the FIFO, so you can get up to four captured values. Set up an interrupt routine on capture and read out until FIFO is empty.
if you are really pressed for time, you can maybe also configure multiple timers, each with a different capture timer--that way #1 fires on the first edge, #2 on the second edge, etc.
But .... before I could read the timer capture value what if a new capture has happened......doesn't it rewrite my FIFO. Since FIFO is 4 bytes deep, and if i fail to read my fifo then I will be losing my data once 4 bytes are full.
Reading in ISR is a good option......How can i stop the isr after 4 bytes receive???
To stop after 4 bytes received in the ISR is
a) a matter of counting how many values you already retrieved (broad smile!)
b) when at entry to the ISR the FIFO_Full flag is set, you know that you've got 4 values (you may even check withn the debugger if this case even happens) At that point disable the capture via API or a control register.
While reading off the FIFO new captured values might appear, but there is no time-conflict and they are scheduled at the end of the queue. Wasn't there a flag that indicated an overrun so that you may check for critical situations?
Oh great....one more thing ......I will be getiing captures at 40k rate captures also happen at the same rate as the same signal is given as capture for timer......Will there be any sort of overwrite??........I guess no as our BUS clock is at 24 MHz