9 Replies Latest reply on Oct 12, 2012 4:00 AM by rama.sai.krishna.vakkantula

    FX3 CYUSB3014 Flag question

    zhao.huawei

      Hi everyone

         

       

         
           The value of flagA is initialized high.and The value of FlagB is initialized low,The value of FlagC is initialized high.and the value of FlagD is initialized low.     the four Flags polarity are low     .   
         
              
         
              
         
           Before download the firmware,the FlagA signal is low,The FlagB signal is low,the Flagc signal is high and the FlagD is high. Why?   
        • 1. Re: FX3 CYUSB3014 Flag question
          rama.sai.krishna.vakkantula

          Basically, we assign these flags to some GPIOs. I am not sure which GPIOs you used with these flags. But before you download the firmware, the default values that you are seeing are the values of those GPIOs.

             

          Thanks,

             

          sai krishna.

          • 2. Re: FX3 CYUSB3014 Flag question
            zhao.huawei

            Hi 

               

            void fx3_DmaCallback_EP2 (
                    CyU3PDmaChannel   *chHandle,
                    CyU3PDmaCbType_t  type,
                    CyU3PDmaCBInput_t *input)
            {
                //uint16_t index;
                CyU3PDmaBuffer_t buf_p;
                CyU3PReturnStatus_t status = CY_U3P_SUCCESS;
                uint8_t curState_p;
                process_stage = 0;
                if (type == CY_U3P_DMA_CB_PROD_EVENT)
                {
                 status = CyU3PDmaChannelCommitBuffer (chHandle, input->buffer_p.count, 0); // breakpoint
            )

               

            ............................................................

               

               

            when PC didn't  send some data ,before exectued breakpoint, I find the flagC signal is below .and  the Polarity is choosed active Low.In other word ,FPGA think that there are some data in the psocker and can read out of  the pscoket.why?

            • 3. Re: FX3 CYUSB3014 Flag question
              zhao.huawei

              Hi

                 

              I am so sorry

                 

              the Flagc signal change to high?why

              • 4. Re: FX3 CYUSB3014 Flag question
                zhao.huawei

                Hi 

                   

                void fx3_DmaCallback_EP2 (
                        CyU3PDmaChannel   *chHandle,
                        CyU3PDmaCbType_t  type,
                        CyU3PDmaCBInput_t *input)
                {
                    //uint16_t index;
                    CyU3PDmaBuffer_t buf_p;
                    CyU3PReturnStatus_t status = CY_U3P_SUCCESS;
                    uint8_t curState_p;
                    process_stage = 0;
                    if (type == CY_U3P_DMA_CB_PROD_EVENT)
                    {
                     status = CyU3PDmaChannelCommitBuffer (chHandle, input->buffer_p.count, 0); // breakpoint
                )

                   

                ............................................................

                   

                   

                After exectued breakpoint I find the flagC signal change to high.In other word ,FPGA think that there arenot some data in the psocker and cannot read out of  the pscoket.I think that there are some data in the pscocket.ls my understanding right?

                • 5. Re: FX3 CYUSB3014 Flag question
                  rama.sai.krishna.vakkantula

                  I Would like to know how you configured the flags on the interface definition of the GPIF II designer.

                     

                  You can configure the flags of slave FX3 to indicate one of the following:

                     

                  Current_thread_DMA_ready/Thread_0_DMA_ready/Thread_1_DMA_ready/Thread_2_DMA_ready/Thread_3_DMA_ready

                     

                  Current_thread_DMA_watermark/Thread_0_DMA_watermark/Thread_1_DMA_watermark/Thread_2_DMA_watermark/Thread_3_DMA_watermark.

                     

                  Current_thread_DMA_ready usage is as follows:

                     

                  Let say FPGA is writing data to FX3. Then it will select the socket/thread by driving address on address lines. Then this Current_thread_DMA_ready indicates the status of the slected socket. Here FPGA is writing data into a producer socket. So this flag indicates whether the socket is free to accept data or not.

                     

                  In case if FPGA wants to read data from FX3 then the same flag indicates the readyness of the active socket. Here in this case a Consumer socket. So it will be asserted if consumer socket has some data in it.

                     

                  Thread_0_DMA_ready/Thread_1_DMA_ready/Thread_2_DMA_ready/Thread_3_DMA_ready - these are dedicated flags for the corresponding sockets/threads irrespective of the address lines.

                     

                  Thanks,

                     

                  sai krishna.

                  • 6. Re: FX3 CYUSB3014 Flag question
                    zhao.huawei

                    Hi

                       

                    Thanks your reply

                       

                    pc------>>usocket-------->>>DMA---------------->>>pSocket------thread

                       

                    FlagA is dedicated to thread0,FlagB is dedicated  to thread1,FlagC is dedicated  to thread2 and so on.But I use two address line to choose address.

                       

                    void fx3_DmaCallback_EP2 (
                            CyU3PDmaChannel   *chHandle,
                            CyU3PDmaCbType_t  type,
                            CyU3PDmaCBInput_t *input)
                    {
                        //uint16_t index;
                        CyU3PDmaBuffer_t buf_p;
                        CyU3PReturnStatus_t status = CY_U3P_SUCCESS;
                        uint8_t curState_p;
                        process_stage = 0;
                        if (type == CY_U3P_DMA_CB_PROD_EVENT)
                        {
                         status = CyU3PDmaChannelCommitBuffer (chHandle, input->buffer_p.count, 0); // breakpoint
                    )

                       

                    ............................................................

                       

                       

                    Q1

                       

                    After CyU3PDmaChannelCommitBuffer () API ,ls it transferred  usocket to psocket

                       

                    Q2

                       

                    if I set polarity active low,i find that the FlagC signal change to high after exectued   CyU3PDmaChannelCommitBuffer () API 

                       

                    if I set polarity active high,i find that the FlagC signal change to low after exectued  CyU3PDmaChannelCommitBuffer () API  

                       

                    I am confused

                    • 7. Re: FX3 CYUSB3014 Flag question
                      zhang.tao

                      I also encountered the same problem.

                         

                      Platform: FPGA---xilinx spartan 6; CYUSB3014(release version,not ES edition)
                      My slave fifo mode U3 design used 3 channels config as follows.

                      the first channel:
                      diretiion producer comsumer endpoint
                      PtoU CY_U3P_PIB_SOCKET_0 CY_U3P_UIB_SOCKET_CONS_1 0x81
                      the second channel:
                      diretiion producer comsumer endpoint
                      PtoU------CY_U3P_PIB_SOCKET_1-----CY_U3P_UIB_SOCKET_CONS_2----0x82
                      the third channel:
                      diretiion producer comsumer endpoint
                      UtoP----CY_U3P_UIB_SOCKET_PROD_1----CY_U3P_PIB_SOCKET_3-----0x82

                      GPIF desiger use FLAG[0] as current thread ready; FLAG[1] as thread 1(channel 1) ready.

                      Then FPGA drive the 3014 interface port with 100MHz clk.Here is the drive sequence in a poll way:
                      1:set thread ID(ctl[11:12],clt[12] is LSB) to thread 0,
                      2:delay 16 clks.
                      3:read FLAG[0] and FLAG[1],
                      then change threadID to thread 1 and thread 3. and there are always 16 clks before read the FLAGs.

                      Thread 0 and Thread 1 performed properly(FLAG showed this thread is ready)
                      But Before Host PC send the package data to thread 3, it also showed it's ready, this will trigger FPGA read on this thread, but the FLAG[0] on thread 3 never become 0. So lead to error which FPGA never stop on read this thread.

                      • 8. Re: FX3 CYUSB3014 Flag question
                        rama.sai.krishna.vakkantula

                        assa,

                           

                        I would recommend you to check the functionlity of your system by using a dedicated flag for TH3.

                           

                        May be you can configure your flag[0] to get the status of DMA_RDY_TH3 always. You can use a seperate GPIO for this purpose, if you have a provision to do thta. Check whether driving the thread ID corresponding to TH3 and flag corresponding to TH3 are working fine.

                           

                        Thanks,

                           

                        sai krishna.

                        • 9. Re: FX3 CYUSB3014 Flag question
                          rama.sai.krishna.vakkantula

                          Are you using the endpoint 0x82 for U to P transfers as well?

                             

                              

                             

                                    

                             

                          UtoP----CY_U3P_UIB_SOCKET_PROD_1----CY_U3P_PIB_SOCKET_3-----0x82

                             

                          Or is it a typo?

                             

                          Thanks,

                             

                          sai krishna.