I suppose that might depend on the bus-clock you have configured.
How is you your drq-signal generated and what does your DMA-setup look like?
Best can be if you upload your project here, so we all can have a look at it.
To do so: in Creator 2.1 Build -> Clean Project
File -> Create Workspace Bundle (minimal)
and finally upload the resulting Zip-archieve here (takes some time after pressing the "post" button)
If you look in the Architecture TRM there is an example of computing the number
of buss cycles to do a burst, inclduing its overhead. Bus clock is the prime limiting
factor during the burst. Search in index for PHUB and DMAC.
N+6 for interspoke DMA transfers
2N+5 for intraspoke DMA transfersN -> Burst counts
When there are more than 1 channel requesting a free DMA Controller, the arbitration phase would take more cycles and it uses Grant allocation Fairness Algorithm for allocation of channels.