5 Replies Latest reply on Oct 13, 2012 6:29 AM by kishore.kumar

    ADC Filter Flush

    glenn.yeager

      When an ADC is configured in continuous mode does calling ADC_DelSig_StopConvert() mean that the ADC's filters need to be flushed again when ADC_DelSig_StartConvert() is called?

        • 1. Re: ADC Filter Flush
          user_14586677

          The below is in the datasheet, but not really complete in my opinion. Seems to infer internal filter charge,

             

          therefore discharge issue as well. Sw cap filters affected by charge I available and leakage when

             

          stopped ? You might want to file a tech case at www.cypress.com to clarify, then share with the forum.

             

           

             

          Continuous sample mode operates as a normal delta-sigmaconverter. Use this mode when
          measuring a single input signal.There is a latency of three conversion times before the first
          conversion result is available.This is the time required to prime the internal filter. After
          the first result, a conversion will be available at the selected sample rate.Do not use this mode
          when multiple signals are multiplexed and measured with  asingle ADC.

             

           

             

          You might run a test case as well on your dev board as another verification.

             

           

             

          Regards, Dana.

          • 2. Re: ADC Filter Flush
            glenn.yeager

            Okay, filed a case but I also did some tests....

               
               

            The ADC is configured as seen in the attached image:

               

            When using the following code:

               

            void main()
            {
                uint8 result = 0;
                uint8 vdacOut = 1;
               
                /* Place your initialization/startup code here (e.g. MyInst_Start()) */
                VDAC8_Start();
                ADC_Start();

                CyGlobalIntEnable;
                EOC_ISR_StartEx(My_EOC_ISR);
               
                ADC_StartConvert();
               
                for(;;)
                {

                }
            }
             

               

            We can see that the EOC of the ADC is triggered every 2.6uS and is high for about 140nS.

               

            According to the configuration with an SPS rate of 384k we should see an EOC every 2.604 uS and the EOC should be high for one ADC clock period according to the data sheet. So with a clock frequency of 6.144 MHz the EOC should be high for 162.76 nS. So far so good.

               
               

            Now if we leave the ADC configuration as is and change the code to...

               

            void main()
            {
                VDAC8_Start();
                ADC_Start();

                CyGlobalIntEnable;
                EOC_ISR_StartEx(My_EOC_ISR);
               
                ADC_StartConvert();
               
                for(;;)
                {
                    if(finished == 1){
                        finished = 0;
                        ADC_StartConvert();
                    }
                }
            }

            CY_ISR(My_EOC_ISR){   
                ADC_StopConvert();
                finished = 1;
            }

               

            We now see that the EOC output is very different. Instead of the EOC continuously triggering it now only triggers twice in a 27.9 uS period. There are two EOC triggers about 2.6 uS apart an they each last about 140 nS, same as above. However after the 2nd EOC there is a 25 uS gap between the start of the next two pulses.

               

            If you measure the time it takes to perform the ADC_StartConvert() operation it comes out to be about 4 uS.

               

            If you measure the time it takes to perform the ADC_StopConvert() operation it comes out to be about 5 uS.

               

            For some reason each operation is being run twice, the _StartConvert() before the EOC and the _StopConvert() after the EOC, so this comes out to (2*4 uS + 2*5 uS) = 18 uS which leaves about 7 uS between the 2 conversions (25 uS - 18 uS).

               

            The data sheet says that the ADC requires 3 conversion cycles to flush the filter so, 3*2.6uS = 7.8uS and this accounts for the extra 7uS seen above.

               

             

               

            So in the end I do believe the filter is flushed when using the ADC_StartConvert() and ADC_StopConvert() API, however I'm not sure why I see multiple triggers at each iteration. Really wish I had my camera so I could give you guys OScope shots =/

               

             

               

            I'll post the project in the next post so you guys can check it out yourselves.

            • 3. Re: ADC Filter Flush
              glenn.yeager

              Here is the project. I'll also update when I hear back from my technical case.

              • 4. Re: ADC Filter Flush
                glenn.yeager

                Wow, they are fast. The official response is that yes upon calling ADC_StartConvert() with the ADC in continuous mode it will require 3 conversion cycles before a conversion can actually take place.

                   

                Hope this helps others.

                • 5. Re: ADC Filter Flush
                  kishore.kumar

                  Refer to "Table 39-17. ADC Conversion Time" of PSoC3 TRM. It talks about conversion time of different modes of configuration.

                     


                  Regards,

                     

                  Kishore.