2 Replies Latest reply on Oct 24, 2012 12:45 AM by takeru.fujishiro

    Question about Synchronous Slave FIFO Read Sequence.

    takeru.fujishiro
          Hello,   
         
          In our system, FX3 and FPGA are connected by Synchronous Slave FIFO interface(32bit bus).   
         
          We have a question about the sequence for performing reads from it.   
         
          If a master(FPGA) starts asserting of SLCS and SLRD simultaneously, is it a problem for a slave(FX3)?   
         
          In Figure3 of the Application Note(AN65974_001-65974.pdf), it begins to assert SLRD after 1 cycle of PCLK from SLCS.   
         
          And, the description about the timing is not found besides the figure.   
         
          Do we have to design according to the timing of this figure?   
         
          Regards,   
         
          kommy2