7 Replies Latest reply on Oct 25, 2012 12:07 AM by ramnath.r.k

    Verilog code output

    hanumanth.vinukonda

      hello, i wrote a verilog program and i sucessfully build it in PSoC creator tool , but now i am not getting how to see the outputs.Please give some solutions regarding my problem....Thanking you in advance :)

        • 1. Re: Verilog code output
          user_1377889

          Did you create a symbol for your Verilog component with the inputs and outputs named accordingly to your verilog-code?

             

           

             

          Bob

          • 2. Re: Verilog code output
            user_1377889

            @Hanu

               

            you might always upload your complete project here for us all to have a look at. Somtimes we find solutions for problems that way.

               

            To do so, in Creator:

               

            Build -> Clean Project

               

            File -> Create Workspace Bundle(minimal)

               

            and then upload here the resulting archive.

               

             

               

            Bob

            • 3. Re: Verilog code output
              kiku

              If you are stuck on how to use the verilog based component in Creator, Refer to this KB article - KBA80958

              • 4. Re: Verilog code output
                ramnath.r.k

                 Hi hanu,

                   

                You would have created a verilog component(verilog code and symbol), i guess.

                   

                1.Please, open the topdesign and drag and drop the component from the defaults tab.

                   

                2.This component would appear in the defaults tab,only when the compnent you have created has been saved. 

                   

                3.Give the Appropriate inputs to the component. Once you are done with this, you can verify the output as you wish, through the pins or through the lcd (writing in to status reg).

                   

                4. If you can upload the project as bob said, we will be able to help you much better.

                   

                Regards,

                   

                Rahul ram

                • 5. Re: Verilog code output
                  hanumanth.vinukonda

                   Hello,

                     

                           I created verilog component (Half adder) and i dragged it and kept in the Topdesign from default tab .If i want to see the output i should give some inputs to the component ,here i strucked i am not getting how to give DIFFERENT inputs and see there corresponding outputs. In quartus tool(Verilog tool) we can see simulation results which is provided by the tool,but here i am unable to get how to proceed . 

                     

                  One more doubt is, if i want to instantiate some modules in a program how to proceed??

                  • 6. Re: Verilog code output
                    user_1377889

                    Hanu, don't you think it would be helpful for us to have a look into your implementation to see what is going on?

                       

                     

                       

                    Bob

                    • 7. Re: Verilog code output
                      kishore.kumar

                      Use control registers for inputting the data and use status registers for reading the output and print it in LCD.

                      • 8. Re: Verilog code output
                        ramnath.r.k

                        Hi ,

                           

                        You can use the lookup table, to provide the inputs to the half adder block. You have to register the outputs of the LUT and loop them back to input. You should make sure that the previous state will be the input to the current state and the next state will be current state + 1.

                           

                        By this way you can switch between the states,

                           

                        00

                           

                        01

                           

                        10

                           

                        11 states.