The Vil, Vih levels limited to .5V off the rails, and 140 mA limit to
invoke latchup. So these specs effectively would be the characterized
process values safeguarded by some margin.
So, if I have voltage of 3.3 + 0.7 (Vddio is of 3.3V) then the signal never enters my pin as the diode shows a very low resistance path for my signal. Am I correct???
The pin clamps to Vdd +Vthdiode, until you feed too much current into
it to either trigger the parasitic SCR mechanism, blowing out Vdd bond
wire internal, or silicon meltdown.
If you do not exceed the current rating then signal looks like a "1" as
it would normally. For the digital case.
For the analog case, Cypress does not have any stated specs on
phase reversal on OpAmps when their inputs are driven outside
their CM range. You would have to test for that.