4 Replies Latest reply on Nov 5, 2012 10:28 AM by userc_43828

    FX3 Layout Support - Microstrip Impedance



      I'm starting a new layout of a design using the FX3 device. I've carefully read the Hardware Guidelines for the FX3 and still cannot understand a couple things:


      1) There is a recommendation of a ~11mil trace width and a 8mil space for the superspeed microstrip lines. From the development kit's fab drawing, I see that there is a bit of a bizarre stackup which yields a 90 Ohm differential impedance (edge-coupled) on these lines with a 12mil trace and 8 mil space. This is all fine, but unfortunately it causes some fairly large 19mil 50-ohm single ended traces! I have a fairly tight design, so I need reasonable ~5-8mil 50 Ohm traces on the top and bottom layers for routing. Is there a reason why the stackup was chosen to give these large traces? Is there a loss factor that I am not considering? I have a stackup that will give the 90 Ohms edge-coupled differential impedance with a ~6/8/6mil microstrip.


      2) B-Type routing: I've decided to use a more rugged full size b-type connector and it is been a fairly painful experience so far. Would it be very unwise to keep the routing (as the attachment shows) on the same side as the connector? I understand that a 'stub' is created from this, but I have no idea on how to gauge the effect. Would it be better to run all of these signals through a set of vias, as recommended (with the ground vias appropriately spaced)? In my mind, it seems that introducing the layer change would be worst than the stub created, but I would definitely like to hear someone's informed opinion. 


      I would definitely like to hear from the experts on this one, thank you!


      Steve M.

        • 1. Re: FX3 Layout Support - Microstrip Impedance

           Please ignore my mistake shown in the picture, the routing from the ESD device to the capacitors is not spaced correctly. 

          • 2. Re: FX3 Layout Support - Microstrip Impedance

             After spending some time reading on the matter, I'm starting to answer my own questions:


            1) I believe there are two main reasons for why a 12/8/12 90 Ohm differential edge-coupled microstrip was used. These have to do with losses and tolerances. A wider trace will have less loss per inch because of the skin-effect at the ~5GHz USB transmit/receive frequencies. Since my trace is only ~500mils long, as opposed to the up to ~3" mentioned in the hardware guide. From some calculations, I was about twice as lossy per inch than the recommended lines. This alone suggests that it is fine to accept a bit more loss due to the 6x shorter trace. The second reason I believe has to do with simple trace tolerances due to etch factor and the fact that a ~+/- 2mil tolerance will effect the impedance a lot less on a 12 mil trace than a 5mil trace. I know you can call out impedances and trace widths to the pcb fab and they'll go through extra work to control it. Nonetheless, it seems smarter to use a wider trace. Comments?


            My thought is to increase the width to a reasonable 10-12mils as suggested and live with the loss of one of my 50 ohm routing layers. I definitely don't want to route 19mil traces (for the GPIF bus, for example) as shown in the DVK gerbers, especially considering that they should be spaced at least 3w (~60mils!) for effective isolation. 


            2) I still don't have an answer to how the stub will effect performance. Attached is a presentation from intel showing a b-type connector being routing against the Cypress recommendation. Pages 6 and 13 show a through hole connector being routed on the same side as the component.. 


            I would highly appreciate any input / experiences from anyone on this!


            thanks - Steve

            • 3. Re: FX3 Layout Support - Microstrip Impedance



              So long as you get the 90 ohm differential impedance then your trace widths are fine. The wider traces will have lower attenuation but the routing distance in your example is small so any attenuation will be minimal. I have routed the trace widths on two pcbs using 6 mil widths and it works well - over slightly longer distances than your example.


              The PCB manufacture will know their own process so if you specifiy 6 mil traces  they will widen them to compensate for any over etching. The only problem with the thinner traces is if you are using heavier  copper on the top and bottom layers then you can get under cutting of the traces.


              For the GPIO/GPIF signals make these 50 ohms but if you find they are two wide then the stackup of the PCB will need looked at. Alternatively if these traces are very short you may not need to imedance match them. Rule of thumb is if the trace delay is 1/6 of the rise time then you don't need to worry about impedance matching


              I  have two USB 3 pcbs made. On one I used vias so that the USB B conector did not have any stubs on the high speed signals. The routing of this was straightforward. On another prototype board the FX3 and USB B connector were on the same side and I wired the traces directly to the connector which created a small stub in the high speed lines. Both pcbs worked well although I suspect that the one with the stubs will be worse for EMC purposes.



              • 4. Re: FX3 Layout Support - Microstrip Impedance



                You've given me amazing news, thank you very much!


                To know that you have successfully implemented these techniques and created a working board is excellent, nothing beats experience in my books :)


                I appreciate this very much,