5 Replies Latest reply on Nov 15, 2012 12:00 PM by user_49271930

    synchronize two or more DMA

    user_49271930

      Hello all.

         

      I can not figure out how to synchronize 2 or more DMA.
      I created a table with the signal(the meander)that is common to all of the DMA.

         

      At the outputs of the registers, I hope to see 2 synchronous meander (F_1000 and S_1000)
      For measurements I added signal the start DMA ( F_1 and S_1 )
      In fact I see the delay 10uS.

         

      My question is:
      Is there a possibility to synchronize the work of two or more DMA  ?

         

      A copy of the screens and the project are attached below.

        • 1. Re: synchronize two or more DMA
          user_78878863

          Can you tell us a little bit more about that the different signals mean in the screen shot? Where did you connect the logic analyzter to?

             

          When I understand this right you habe a table in RAM, and transfer its values into both control registers, and then check the two lowest bits with the logic analyzer. And you expect them to be in sync with each other, since the DMA request inpuit is feed the same signal.

             

          It might be that your bus clock is too slow. You trigger the DMA with a 4MHz signal, and have a bus clock of 24MHz. This means each DMA request has only 3 bus cycles to finish (6 cycles for both DMAs), and this is way shorter than what the DMA needs. According to the PSoC3 TRM, a DMA transfer needs 6+n cycles. And since you have 2 DMAs fighting for resources, you can have strange results.

             

          Apart from that: since there is only a single DMA controller available, and you want to have two transfers between the same target and source (memory to peripheral), they will always be executed one after another, and not in parallel.

          • 2. Re: synchronize two or more DMA
            user_14586677

            If the targets are on the same spoke then arbitration will occur.

               

             

               

            Per TRM -

               

             

               

            When both the CPU and DMAC request access to the
            same spoke on  PHUB at the same time, the CPU
            takes the higher priority by default. The PHUB
            manages the arbitration between the DMA channels
            and the CPU and DMAC manages arbitration
            between various DMA channels. For more
            information, see  PSoC®  3, PSoC®  5 Architecture
            TRM.

               

             

               

            So you would double buffer the DACs to synch them.

               

             

               

            Regards, Dana.

            • 3. Re: synchronize two or more DMA
              user_49271930


              Thank you for your answers!
              Channels of the analyzer connected as signed:
              DMA_1:
              channel 4 of the analyzer is connected to Pin 2.1 (S_1)
              channel 6 of the analyzer is connected to Pin 2.3 (S_1000)

                 

              Under each channel I put the same channel from DMA_2:

                 

              channel 5 analyzer is connected to Pin 2.0 (F_1)

                 

              channel 7 of the analyzer is connected to Pin 2.2 (F_1000)

                 


              This is a simple test signal for the analysis of signal delay:

                 

              bit0 - start signal repeats every thousandth signal drq.

                 

              bit1 - meander.

                 

              In reality this will be 2 DAC and 8 digital signals (ControlReg) which should work synchronously.

                 

              _____________________________________________________________________________________________________

                 

              I know, in General terms, how does the DMA work and  I expected this result.

                 

              I planned to compensate for the time shift with the help of the shift register, if he does not change in time (up to 30 minutes).
              But I'm worried that the work of the CPU will cause instability and will cause further out of sync. This, too, says danaaknight.
              My problem was divided into 2 parts:

                 

              - to ensure a guaranteed simultaneous launch

                 

              - to ensure detection of ( at least ) being out of sync with long work (10-30 minutes)

                 

              Now I plan to solve at least the first part.
              But i could think of nothing except the shift register. May be there is another solution?
              If I'm lucky, I'll share the solution.
              p.s. I did not understand the idea of a double buffer the DACs ((
               

              • 4. Re: synchronize two or more DMA
                user_14586677

                Use the strobe mode for the DAC, and strobe is fed by DMA complete

                   

                signal from both channels. So OR the two nrq's out of the DMA (enable them

                   

                first, maybe set "D's with them), then feed that to both DAC strobes.

                   

                 

                   

                Strobe Mode

                   

                This parameter selects whether the data is immediately written to the DAC when the data is
                written into the VDAC8 data register. This mode is enabled when the Register Write option is
                selected. When the External option is selected, a clock or signal from the Digital components or
                control register controls when the data is written from the DAC register to the actual DAC.

                   

                 

                   

                Double buffering generally refers to 2 registers, one is fall thru to compnent, like a DAC, and this

                   

                registers input comes from a clocked/strobed register. Allows one to write data to input register,

                   

                then with a synch signal clock that into the outpuit register to update the component, like a DAC

                   

                in synch with other components fed the same synch clock..

                   

                 

                   

                Regards, Dana.

                • 5. Re: synchronize two or more DMA
                  user_49271930

                  I see that the shift between the signals DMA stable over time, but its value depends on the number of the components used (for example the clocks).
                  Until I decided to use a simpler method:
                  I сооздам table for each DMA.

                     

                  Signal in each table will be shifted by a certain number of clock cycles.

                     

                  This value I pick up through experience, when all of the components have already been created.
                  An example of a tables:
                  #define TABLE_SIZE 10  
                  CYCODE const uint8 Dig_Table2[TABLE_SIZE]=
                  {1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
                  CYCODE const uint8 Dig_Table1[TABLE_SIZE]=
                  {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
                  I hope picture helps to understand it.