4 Replies Latest reply on Nov 28, 2012 6:25 AM by rajivv_36

    M8C_Reset - CY8C29666-24ltxi




      I'm working on a project with CY8C29666-24LTXI.


      I'm trying to reset the psoc with the macro M8C_Reset.


      After the reset, the IMO clock of the psoc is out of tolerance, not calibrate.


      Have you an explanation?


      Condition of use:


      U = 3.3V

        • 1. Re: M8C_Reset - CY8C29666-24ltxi

          This might help -




          Your measurement of IMO occurs after settling times ?


          Regards, Dana.

          • 2. Re: M8C_Reset - CY8C29666-24ltxi

            Are you performing an XRES(from technical manual) -




            29.4.2 External Reset


            An External Reset (XRES) is caused by pulling the XRES
            pin high. The XRES pin has an always-on, pull down resis-
            tor, so it does not require an external pull down for operation
            and can be tied directly to ground or left open. Behavior after
            XRES is similar to POR.


            During XRES (XRES=1), the IMO is powered off for low
            power during start-up. Once XRES deasserts, the IMO is
            started (see Figure 29-4). How the XRES configures register
            reset status bits is shown in Table 29-1.




            Regards, Dana.

            • 3. Re: M8C_Reset - CY8C29666-24ltxi

              Also found this in tech reference manual -




              8.3.1 Trimming the IMO


              An 8-bit register (IMO_TR) is used to trim the IMO. Bit 0 is
              the LSB and bit 7 is the MSB. The trim step size is approxi-
              mately 80 kHz.


              A factory trim setting is loaded into the IMO_TR register at
              boot time for 5V ± 0.25V operation, except for the
              CY7C603xx, which is 3.3V ± 0.25V. For operation in the volt-
              age ranges of 3.3V ± 0.3V and 2.7V ± 0.3V, user code must
              modify the contents of this register with values stored in
              Flash bank 0 as shown in  Table 3-11 on page 77. This is
              done with a Table Read command to the Supervisory ROM.




              Regards, Dana.

              • 4. Re: M8C_Reset - CY8C29666-24ltxi

                I don't use the external reset. 


                To reset the psoc, I use the macro M8C_Reset who is:


                asm("mov A, 0\nSSC");




                So, it calls the Supervisory System Call SSC with 0x00 in accumulator.


                It dones a "SWBootReset".


                So the firmware start with the "boot.asm" (inside, there is the call to load the Trim value of the clock, I think??).




                I check the clock few seconds after the psoc is reset, so the clock must be stable (and is stable).


                The issue is that the clock is not 24MHz but about 26MHz.


                Thanks for your help.


                (I resolve the problem by a POR : I say to the PSOC that the power is 5V and it does a POR:






                //M8C_Reset; //BUG find after reset, clock 24MHz is false







                • 5. Re: M8C_Reset - CY8C29666-24ltxi

                  There was issue with M8C_reset. The solution is simple. Just reset MVI pointers before doing software reset as shown below-


                  MVR_PP = 0x00;  //MVI read pointer


                  MVW_PP = 0x00; //MVI write pointer








                  Rajiv Badiger