There is an encyclopeida of replies to cover this toipic.
CMOS has a number of parasitic There is an encyclopedia of replies to cover this topic.
CMOS has a number of parasitic devices, normally “hidden” when things are biased and
started upin the right sequence.
My recommendation is to post a tech case, hopefully which will get looked at by silicon
designer, for an answer. Most datasheets now have specific sections of specs regarding
power sequencing, however missing explicit descriptions as to why, what is actually
CMOS has “well isolation” techniques, keeping devices from interacting, but to the best
of my knowledge, they are all accompanied by parasitic devices that, under the right
circumstances, rear ugly heads, like the parasitic SCR mechanism that can produce a short
internally from Vdd to Vss and typically blows open the bond wire in Vdd or Vss to the
lead frame. Process technology actually takes into account the SCR trigger gain, beta, to
minimize its effects.
How to pose a tech case?? I have couple of things that are to be confimed with Cypress Engineers.
I don't know whether Cypress will answer some small queries.
Have you got an answer for this?