1 Reply Latest reply on Dec 11, 2012 10:13 AM by rama.sai.krishna.vakkantula

    Is that can be possible 10bit data slave-fifo mode ?

    lee.carter

       hi

         

      i have working slave fifo in streamin example with fpga.

         

      but it's just only 8bit data like following that.

         

       

         

       

         

      NET "clk"  LOC = "P11" ;

         

      NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;

         

       

         

      NET "flagd" LOC = P15;

         

      NET "flaga" LOC = P13;

         

      NET "faddr<0>" LOC = P47;

         

      NET "faddr<1>" LOC = P51;

         

      NET "fdata<0>" LOC = P7;

         

      NET "fdata<1>" LOC = P10;

         

      NET "fdata<2>" LOC = P12;

         

      NET "fdata<3>" LOC = P14;

         

      NET "fdata<4>" LOC = P17;

         

      NET "fdata<5>" LOC = P20;

         

      NET "fdata<6>" LOC = P23;

         

      NET "fdata<7>" LOC = P25;

         

      NET "gstate<0>" LOC = P137;

         

      NET "gstate<1>" LOC = P135;

         

      NET "gstate<2>" LOC = P132;

         

      NET "gstate<3>" LOC = P131;

         

      NET "slrd" LOC = P24;

         

      NET "sloe" LOC = P40;

         

      NET "slwr" LOC = P21;

         

       

         

      So can i expansion data bit in slavefifo mode in fx2lp 56pin chips ?