We are implementing new firmware in our FX2 chip. Part of the data flow requires access to the Slave FIFO from both external logic and the firmware. Using the EZ-USB TRM Revision D reference and following Section 9.3.8 I've been able to edit the data in the FIFO that was written initially by external logic (our FPGA). However, in assembling the IN packet to the host in the FIFO, we'd like to write header data to the FIFO *before* the external logic writes (and hopefully appends) the FPGA data. Currently, I find that the external logic/FPGA always overwrites the header data written to the FIFO by the firmware. Is there a way to control the FX2 internal FIFO pointer that tracks the writing of FIFO data by external logic, such that I could advance it the header length through firmware before the FPGA-based Slave FIFO write?