< .... continued>
From the attached image, you can calculate VC1, VC2 and VC3 clocks for a given CSD resolution and Scan speed.
So, if you have set the RX8 clock input to be VC2 with a frequency of 150 KHz in global parameters (SysClk = 24 MHz, VC1 = Sysclk/16, VC2 = VC1 / 10) and have a CSD configured at 12 bit resolution and Normal scan speed. During CSD_Start() API execution, the values of VC1, VC2 and VC3 are changed as 4, 8 and 128 respectively. As a result of this, your RX8 input clock becomes 750 KHz (VC1 = Sysclk/4, VC2 = VC1 / 8) instead of the intended 150 KHz. Thus completely destroying the UART baud rate. With SmartSense the situation worsens, as these divider values are not exposed to user and they change for each sensor.
- Use external clock option for UART (using ROW_INPUT_x or ROW_OUTPUT_x lines and routing clock through a pin)
- For CSD/CSDADC UMs, find out the VC1, VC2 and VC3 dividers based on resolution and scan speed. Accordingly, calculate the baud rate of the UART in the CY8C21x34 family and use the same baud rate on the other side.
This issue is not confined to UART alone. It applies to all the sources from digital blocks to Interrupts (like VC3 ISR) which use these system clock dividers. UART was chosen as it is the most common issue customer end up with while trying to transmit the sensor status over UART lines.
CSD_Settings_For_VC.jpg 122.1 K
Friends, the previous post from me, is not valid for CY8C21x34 devices. But, you can use it in PSoC 1 families where sufficient digital blocks are available even after placing capsense module.