CY8C21x34 Family - UART not working properly with CSD

[MeenakshiR_71]

Issue/Problem:

   

I am using hardware UART (RX8 or TX8 UM) with CapSense CSD/SmartSense/CSDADC UM in CY8C21x34 family of PSoC 1 devices. My UART is not working properly.

   

Cause:

   

Most probable cause is the clock input of RX8/TX8 UM. If the clock input is any of the VC1, VC2 or VC3 dividers, then the intended baud rate obtained from those clock sources for the UART will be destroyed during program execution. The reason being based on Resolution and Scanning speed CSD/CSDADC/SmartSense UM modifies VC1, VC2 and VC3 dividers. The information and details on how they impact can be found in the UM datasheet (below figure).

       

So if you set the input clock of RX8 as VC2 and fix a baud rate of 150 ksps (SysClk = 24MHz, VC1 = Sysclk/16; VC2 = VC1/10). With a CSD resolution of 12 bit and normal scan speed, your baud rate changes to 750 ksps (Sysclk = 24, VC1 = Sysclk/4, VC2 = VC1/8). And this happens when CSD_Start() API is called. Worser would be using SmartSense, where the values of these dividers are not exposed to user and they change with each sensor.

   

Solution/Possible workarounds:

   

    
1. Use external Clock option (ROW_INPUT_x lines) for the input clock and route the clock to a pin.
    
2. If using CSD/CSDADC, then based on the resolution and scan speed selected for the design calculate the baud rate in CY8C21x34 and tune the other end UART RX/TX to the baud rate obtained.
   

   

This bug is not confined to UART, it is valid for all the sources from digital block to interrupts like VC3 ISR which uses these system clock dividers. UART was taken as an example as it is the most common issue faced by customers trying to communicate the CSD button status over UART lines.

   

Please feel free to add your thoughts on other possible workarounds too.

[MeenakshiR_71]

< .... continued>

   

From the attached image, you can calculate VC1, VC2 and VC3 clocks for a given CSD resolution and Scan speed.

   

So, if you have set the RX8 clock input to be VC2 with a frequency of 150 KHz in global parameters (SysClk = 24 MHz, VC1 = Sysclk/16, VC2 = VC1 / 10) and have a CSD configured at 12 bit resolution and Normal scan speed. During CSD_Start() API execution, the values of VC1, VC2 and VC3 are changed as 4, 8 and 128 respectively. As a result of this, your RX8 input clock becomes 750 KHz (VC1 = Sysclk/4, VC2 = VC1 / 😎 instead of the intended 150 KHz. Thus completely destroying the UART baud rate. With SmartSense the situation worsens, as these divider values are not exposed to user and they change for each sensor.

   

Possible Solutions/Workaround:

   

    
1. Use external clock option for UART (using ROW_INPUT_x or ROW_OUTPUT_x lines and routing clock through a pin)
    
2. For CSD/CSDADC UMs, find out the VC1, VC2 and VC3 dividers based on resolution and scan speed. Accordingly, calculate the baud rate of the UART in the CY8C21x34 family and use the same baud rate on the other side.
   

   

This issue is not confined to UART alone. It applies to all the sources from digital blocks to Interrupts (like VC3 ISR) which use these system clock dividers. UART was chosen as it is the most common issue customer end up with while trying to transmit the sensor status over UART lines.

[Anonymous]

One more option is to derive the UART clock from a PWM module. PWM input clock should be set to system clock. Setting the period value of the PWM configures the UART baud rate. 

       

However, this method consumes 1 or 2 digital blocks .

[Anonymous]

It turns out that after placing CSD, there is only 1 digital block left for RX or TX implementation. There is no place for PWM module . 

       

Friends, the previous post from me, is not valid for CY8C21x34 devices. But, you can use it in PSoC 1 families where sufficient digital blocks are available even after placing capsense module.