7 Replies Latest reply on Jan 10, 2013 9:38 AM by prajith.cheerakkoda

    output enable setting

    lee.carter

       Hi

         

      I want make output direction partially out  and in. 

         

      When i set to OEA=oxff, as i know, this direction is out. 

         

      But i think another pin also have same direction.

         

      How can i set partially?

         

       

         

      Also what is IOA ?

        • 1. Re: output enable setting
          gaya

           Hi,

             

           

             

          I believe this is what you are looking for: in portA , you want some of the pins to act as O/P and some other pins as I/P pins.

             

          SAy, if you want port A.0 to act as O/P and rest of the pins as input, then you can assign:

             

          OEA = 0x01; // only portA.0 is enabled as O/P

             

          Similarly, if you want, say portA.0, 3, 5 as O/P pins, then

             

          OEA = 0x29;  //portA.0,3,5 enabled as O/P pins

             

           

             

          OEA is the O/P enable register for portA. i.e. by setting the appropriate bit in OEA, the appropriate bit of portA can be configured as O/P.

             

          Whereas, IOA reflects the portA status. If you want to assign any particular value to O/P pin of portA, then assign the particular value to the approriate bit of IOA. Similarly, to read the value at the input pin of portA, you can read it from the appropriate bit of IOA.

             

          Say, if you want to make

             

           - portA.0 as O/P pin and make it high

             

           - PortA.1 as I/P pin and read its status

             

          then

             

           OEA = 0x01; //portA.0 is enabled as O/P pin

             

           IOA |= 0x01; // set portA.0 as high

             

           <VAR> = IOA & 0x02; //read status of portA.1

             

          I believe this is what you are looking for.

             

           

             

          Regards,

             

          Gayathri

          • 2. Re: output enable setting
            prajith.cheerakkoda

            Hi,

               

            An IOA is a register. Values written to IOA appear on the pins which are configured as outputs; values read from IOA indicate the states of the 8 pins, regardless of input/output configuration. See IOx register on page  183 of TRM .

               

            An OE x register (where x is A, B, C, D, or E), which sets the input/output direction of each of the 8 pins (0 = input, 1 = out-put). So, you can set the pins based on your requirements.

               

            Regards

               

            Prajith

            • 3. Re: output enable setting
              lee.carter

               Hi 

                 

              For acutually, If i want make input direction IFCLK pin and SLWR in  FX2LP 128AXC, then what am i do for setting?

              • 4. Re: output enable setting
                lee.carter

                  Hi 

                   

                For acutually, If i want make input direction IFCLK pin and SLWR in  FX2LP 128AXC, then what am i do for setting?

                   

                 

                   

                i think SLWR and IFCLK is not assigned as Port Pin. Also So many pins are also not assigned.

                   

                 

                   

                except for PA#,PB#,etc...Port Pins.

                   

                 

                   

                So, how i do such as IFCLK SLWR, FLAGA ... etc pins?

                • 5. Re: output enable setting
                  prajith.cheerakkoda

                   Hi,

                     

                  SLWR is an input signal to FX2LP,SLWR pin should be asserted by the master in order to write data to the FIFO. In synchronous mode (IFCONFIG.3 = 0), data on the FD bus is written to the FIFO (and the FIFO pointer is incremented) on each rising edge of IFCLK while SLWR is asserted. In asynchronous mode (IFCONFIG.3 = 1), data on the FD bus is written to the FIFO (and the FIFO pointer is incremented) on each asserted-to-deasserted transition of SLWR. By default, SLWR is active-low; its polarity can be changed via the FIFOPINPOLAR register.

                     

                   

                     

                  IFCLK can be used either as external clock source or for providing clock to external device. IFCONFIG.7 selects between internal and external sources: 0 = external, 1 = internal. If an external IFCLK is chosen, it must be free running at a minimum frequency of 5 MHz. In addition, in order to provide synchronization for the internal endpoint FIFO logic, the external IFCLK source must be present before the firmware sets IFCONFIG.7 = 0.

                     

                  FLAG pins are out put pins which provides the status of  the EZ-USB’s FIFOs.

                     

                  Regards

                     

                  Prajith

                  • 6. Re: output enable setting
                    lee.carter

                    Ok i see.

                       

                    Thanks a lot. 

                    • 7. Re: output enable setting
                      prajith.cheerakkoda

                       You are welcome