The I/O specs are in three parts one the max Voh, Vol at a given Ioh, Iol
you will experience, a port limitation total for even or odd numbered pins, and
a guarenteed Iol, Ioh levels for a Vdd.
So ( example a GPIO port even pin ) -
1) I can sink 20 mA into a pin, driven low, as long as total Iol < 60 mA in all
even pins in that port.
2) If I sink 20 mA into a pin the pins Vol will be <=.75 V
IOH1 - High Output current on Port 0 ==>
- Port 0 pins can source a Min of 0.01 mA (mostly the consumption of the GPIO cell when pin state is 1, without any external loads).
- Port 0 pins can source a Max of 1 mA (limitation of the high side MOS in the GPIO cell)
- The above results are guranteed for VDD > 3.1 V and total current sourced by all I/Os should not exceed 20 mA - this is a limitation from the VDD pad in the chip
IOH2 - High output current on Port 1 pins ==> Similar to above, the total of 20 mA applies to the entire chip not specific port. 20 mA source current is the MAX that the VDD pad in the device can take/withstand.
IOL - Low output current ==>
- All I/Os can sink a Max of 20 mA current each at VDD > 3.1 V (this is limitation of the Low side MOS in the GPIO cell)
- Since there are 2 GND pads inside this device, there are 2 groups of Pin for total current sink for the Chip. P0_2, P1_2, P1_3, P1_4 are connected to one GND pad and they can together sink a max of 60 mA and the remaining GPIOs can together sink a Max of 60 mA (this 60 mA is from the GND pad in the chip, because of 2 GND pads, you get two seperate limits). Provided VDD >3.1 V.
Hope this helps. Similarly there are specs for VDD<3.1 V given in Page 22.
Woua ! Congratulation !
Thank you very much, it 's very clear, good job and now thanks to you i can know plainly the electrical spécification of the CY8C201A0.