With the UDB counter such a operation should be possible. You can configure the counter for up/down mode, With Counter_WriteCompare you can set the compare value. This compare value goes high after a clock cycle.
You can also have interrupt attached to interrupt out of counter. On interrupt you can write a new period, new compare value as well as stop the counter in the isr.
You can also use the feature of "Reload Counter" to initialize the Counter in hardware (without the CPU intervention) upon conditions such as Capture, Compare Match or upon Terminal Count.
It is very much possible with the creation of a custom component using the verilog and datapath. It would consume the same amount of resource as that of the counter component in the creator infact. I don't understand how the compare feature of a counter would solve this.