I am nvSRAM Applications Engineer from Cypress. Thanks for your post. I would like understand your ICC1 validation methodology in details so that I can provide more approproate answer for your concern.
As per datasheet spec of ICC1=75mA@ tRC=25 ns; This spec is charecterized with IOUT=0 mA load condition, which means no external load (either capacitive or resistive) is expected on device IO pins. Which means, even if controller doesn't read nvSRAM I/O state during read operation, it still adds some capacitive load to databus due to its own pin capacitance + trace capacitnace.
Ideally, no external device or probe points should be connected to nvSRAM IOs for ICC1 mesure during read.
Altenatively you can measure ICC1with OE = disable (HIGH), and then add dynamic current component due to switching of CMOS device I/O pins with its own pin load capacitance (14 pf Max).
You can use formula = 0.5*C*V*V*f *N to calculate the dynamic power cosumption then divide by operating voltage to measure the dyncamic average swithiching current for N no of IOs.
So dynamic current in this case will be = (0.5*C*V*V*f*16)/V or 0.5*C*V*f*N = 0.5*14*[10*10^(-12)]*3.6*[40*10^6]*16 = 16.13 mA. So if you get ICC1 <=68.9 mA with OE =disable then device is well within the spec.
Hope this helps. Please let me know if you have any question.
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The power numbers specified in the datasheet are the core power consumption of the device, when Iout is 0 or no load is connected.
Typically when a read happens, the memory drives the data, so when the memory drives the data, there is current consumption from the chip. This is not accounted for in the datasheet.
The article has the details to calculate the power consumption - http://www.cypress.com/?id=4&rID=40611
Let us know if this helps.