When non synchronous signals or signals which are not actual clocks are routed as datapath clock, the synthesizer would throw an error telling that, it has to get through the clk enable block to be routed appropriately. What precisely needs to be done is the following,
There is an instance in which we can make the sync mode false and put in that clock signal as an input and take the asynchronous clock as output. That is precisely done below.
Now, we have to wire the a_clk to the datapath.
The synthesizer would yet throw a warning telling us that an asyncronous path exist. We can ignore that warning, because that is what we want:-).
Regards, Rahul Ram