This is my understanding of your data path based on your description.
FPGA acting as master -> FX3 Slave FIFO interface -> PC
You are using Thread_0_DMA_Ready as a flag to indicate the status of thread 0.
I assume that you are using Socket 0 on the GPIF II side as producer socket.
When FPGA is writing data to producer socket then Thread_0_DMA_Ready only changes when the buffer allocated to that socket is filled.
So it will let you know when you need to stop writing data to GPIF II interface.