2 Replies Latest reply on Feb 19, 2013 3:30 AM by user_1377889

    clolck 16Mhz

    wilson.fernando

       Hello

         

       

         

      I need to generate a clock of 16MHz r, however appears a dc signal, this looks on an oscilloscope. But not for me.

         

       

         

      Why psoc when working at high frequency pacer not have good performance

        • 1. Re: clolck 16Mhz
          sridhar.m

           Hello ferchorr,

             

          How r u generatig the 16 MHz clock?  what is the source of clock used ? Please attach your project so that we can have a look.

             

          - srim

          • 2. Re: clolck 16Mhz
            user_1377889

            Easiest and most precise would be to run BusClock at 48MHz and define a clock of 16MHz which then will use internally a divider of 3. Alternatively you can set the PLL frequency to 48MHz, keep the BusClock at 24MHz and defining a clock with 16MHz derived (unsynchronized) from PLL. Lastly you are free to use a 48MHz clock as input to a Timer and divide it by three.

               

            The trick is that you need an internal clock running at a multiple of your desired 16MHz (a reference of 32MHz instead of 48MHz would have worked as well).

               

            I hope you can see now that the clock definition and distribution in a PSoC is more flexible than you have seen so far.

               

             

               

            Happy clocking

               

            Bob