I was driving a clock out of the pin. Basically I am connecting 8 not gates back to back to get a delay from input to output.
But when I connect the output of clock and output after 8 not gates there is no delsy found. I think the Creator is intelligent enough to optimise the design i guess. How can I generate a delay using gates. Or can I stop Creator optimising the topdesign.
Yes, Looks like the creator is optimising out. Not sure if there is way to disable the optimization for the components. Here is a similar post which talked about this kind of problem : http://www.cypress.com/?app=forum&id=2492&rID=75733