The max frequency of interrupts in psoc5 depends mainly what you actually do within the ISR.
The TRM for PSoC5 (Pg. 50) says that at least 12 cycles latency is needed to enter the ISR, every Instruction will need some cycles too, so much for the frequency.
Usually developers are intrested on the reaction-time on a signal, not on max frequency. So I'd like to ask what you want to perform with a high interrupt rate.
My idea is audio buffer operation - like filter, shaper, delay, multiply .....
I would suggest to use something like ADC, DFB (Digital Filter) and the use of DMA to transfer information from one block to the other. That will not use any CPU and runs as fast as the ADC will.
As bob mentioned DMA a good choice in case of filter, which also
can be used for delay, eg. allpass etc...becuse this can all be HW
But if you have to do processing the filter cannot handle, ISR effectiveness is
best when you do nothing more than set a flag in ISR and exit. That way, by
not calling any f()'s within ISR you dont get a lot of stack push, hence MIPs
wasted. It's generally a good practice to handle ISR response this way.