1 Reply Latest reply on Mar 14, 2013 6:09 AM by user_14586677

    a question on wakeup from standby

    jingwei.tan

      Hi,

         

      I am using CY8C20346A, to save power, M8C standby is used, when a gpio interrupt come, M8C will be wakeup after for a while. in TRM "Wakeup Sequence" in page83, there are T0, T1, T2, T3, T4 points.

         

      After wakeup, I need to use core/GPIO/I2C slave/capsence/timer0 modules,  can I start working after T0 or need to wait until T4?

         

      Thanks.
      BR.
      999

        • 1. Re: a question on wakeup from standby
          user_14586677

          Looks like T4, from the TRM -

             

           

             

          11.4.2 Wakeup Sequence

             


          When asleep, the only event that wakes the system is an
          interrupt. The Global Interrupt Enable of the CPU Flag regis-
          ter does not need to be set. Any unmasked interrupt wakes
          the system up. It is optional for the CPU to actually take the
          interrupt after the wakeup sequence.

             


          The wakeup sequence is synchronized to the taps from the
          wakeup timer (running on IMO clock). This allows the flash
          memory module enough time to power up before the CPU
          asserts the first read access. Another reason for the delay is
          to allow the IMO, bandgap, and LVD/POR circuits time to
          settle before actually being used in the system. As shown in
          Figure 11-2, the wakeup sequence is as follows.

             


          1. The wakeup interrupt occurs and the sequence is initi-
          ated at INT (shown in Figure 11-2 on page 83). The
          interrupt asynchronously enables the regulator, the
          bandgap circuit, LSO, POR, and the IMO. As the core
          power ramps, the IMO starts to oscillate and the remain-
          der of the sequence is timed with configurable durations
          from the wakeup timer.
          2. At T1, the bandgap is sampled and the flash is enabled.
          3. At T2, the flash is put in power saving mode (idle).
          4. At T3, the POR/LVD comparators are sampled and the
          CPU restarts.

             

           

             

          Regards, Dana.