The FX3 FIFOs are associated with sockets. Sockets on the GPIF II side are similar to endpoints on the USB interface.
FX3 provides four physical hardware threads for data transfer over the GPIF II. At a time, any one socket is mapped to a physical thread. By default, PIB socket 0 is mapped to thread 0, PIB socket 1 is mapped to thread 1, PIB socket 2 is mapped to thread 2 and PIB socket 3 is mapped to thread 3.
Note that if data is to be transferred from the Slave FIFO interface to the USB interface, then P-port is the producer and USB is the consumer, and vice-versa. So if data is to be transferred in both directions over the Slave FIFO interface, two DMA channels should be configured, one with P-port as the producer and another with P-port as the consumer.
Coming to descriptor,
GPIF II state transitions occur based on control input signals. Control output signals are driven by GPIF II state transitions. The behavior of the state machine is defined by a descriptor, which is designed to meet the required interface specifications. The GPIF II descriptor is essentially a set of programmable register configurations.
thank you for you answer. If the descriptor works in DMA channel,when the data is 32bits or 4bits,but the size of DMA buffer is 1024bits ,the buffer is not full , SO if the consumer endpoint can use the descriptor to transfer ?
Sorry that I did not get your question clearly.
Could you please explain little bit more about your requirement or the question that you posted above.